drm/bridge: tc358767: Introduce tc_set_syspllparam()

[sfrench/cifs-2.6.git] / drivers / gpu / drm / bridge / tc358767.c

diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index b60cd3607f4f10e9c015785d7386eaa87d48716c..40dea1b5e28a94af6bf01b2006ae8d271e283057 100644 (file)
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -556,35 +556,40 @@ static int tc_stream_clock_calc(struct tc_data *tc)
        return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768);
 }
 
-static int tc_aux_link_setup(struct tc_data *tc)
+static int tc_set_syspllparam(struct tc_data *tc)
 {
        unsigned long rate;
-       u32 dp0_auxcfg1;
-       u32 value;
-       int ret;
+       u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
 
        rate = clk_get_rate(tc->refclk);
        switch (rate) {
        case 38400000:
-               value = REF_FREQ_38M4;
+               pllparam |= REF_FREQ_38M4;
                break;
        case 26000000:
-               value = REF_FREQ_26M;
+               pllparam |= REF_FREQ_26M;
                break;
        case 19200000:
-               value = REF_FREQ_19M2;
+               pllparam |= REF_FREQ_19M2;
                break;
        case 13000000:
-               value = REF_FREQ_13M;
+               pllparam |= REF_FREQ_13M;
                break;
        default:
                dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
                return -EINVAL;
        }
 
+       return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam);
+}
+
+static int tc_aux_link_setup(struct tc_data *tc)
+{
+       int ret;
+       u32 dp0_auxcfg1;
+
        /* Setup DP-PHY / PLL */
-       value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
-       ret = regmap_write(tc->regmap, SYS_PLLPARAM, value);
+       ret = tc_set_syspllparam(tc);
        if (ret)
                goto err;
 
@@ -843,7 +848,6 @@ static int tc_main_link_enable(struct tc_data *tc)
 {
        struct drm_dp_aux *aux = &tc->aux;
        struct device *dev = tc->dev;
-       unsigned int rate;
        u32 dp_phy_ctrl;
        u32 value;
        int ret;
@@ -871,25 +875,7 @@ static int tc_main_link_enable(struct tc_data *tc)
        if (ret)
                return ret;
 
-       rate = clk_get_rate(tc->refclk);
-       switch (rate) {
-       case 38400000:
-               value = REF_FREQ_38M4;
-               break;
-       case 26000000:
-               value = REF_FREQ_26M;
-               break;
-       case 19200000:
-               value = REF_FREQ_19M2;
-               break;
-       case 13000000:
-               value = REF_FREQ_13M;
-               break;
-       default:
-               return -EINVAL;
-       }
-       value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
-       ret = regmap_write(tc->regmap, SYS_PLLPARAM, value);
+       ret = tc_set_syspllparam(tc);
        if (ret)
                return ret;