drm/amdgpu: Add Unique Identifier sysfs file unique_id v2

[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / powerplay / hwmgr / vega20_hwmgr.c

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index d18f34d4a51e17a4ef5f07875e25b2abe80b9fe5..f27c6fbb192ed20133982db6df494893939f482a 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -324,6 +324,8 @@ static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr)
 static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 {
        struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
+       struct amdgpu_device *adev = hwmgr->adev;
+       uint32_t top32, bottom32;
        int i;
 
        data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
@@ -393,6 +395,14 @@ static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
                        ((data->registry_data.disallowed_features >> i) & 1) ?
                        false : true;
        }
+
+       /* Get the SN to turn into a Unique ID */
+       smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32);
+       top32 = smum_get_argument(hwmgr);
+       smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32);
+       bottom32 = smum_get_argument(hwmgr);
+
+       adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
 }
 
 static int vega20_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)