Merge drm/drm-next into drm-misc-next

[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / pm / powerplay / hwmgr / vega20_hwmgr.c

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
index 33f3d97921812b5f389f90c16ea3d824cfcd0397..0d4d4811527c641a030ba3f0a6663dcbd1b35b95 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
@@ -1554,26 +1554,23 @@ static int vega20_set_mclk_od(
        return 0;
 }
 
-static int vega20_populate_umdpstate_clocks(
-               struct pp_hwmgr *hwmgr)
+static void vega20_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr)
 {
        struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
        struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table);
        struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table);
 
-       hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value;
-       hwmgr->pstate_mclk = mem_table->dpm_levels[0].value;
-
        if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
            mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
                hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
                hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
+       } else {
+               hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value;
+               hwmgr->pstate_mclk = mem_table->dpm_levels[0].value;
        }
 
-       hwmgr->pstate_sclk = hwmgr->pstate_sclk * 100;
-       hwmgr->pstate_mclk = hwmgr->pstate_mclk * 100;
-
-       return 0;
+       hwmgr->pstate_sclk_peak = gfx_table->dpm_levels[gfx_table->count - 1].value;
+       hwmgr->pstate_mclk_peak = mem_table->dpm_levels[mem_table->count - 1].value;
 }
 
 static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr,
@@ -1752,10 +1749,7 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
                        "[EnableDPMTasks] Failed to initialize odn settings!",
                        return result);
 
-       result = vega20_populate_umdpstate_clocks(hwmgr);
-       PP_ASSERT_WITH_CODE(!result,
-                       "[EnableDPMTasks] Failed to populate umdpstate clocks!",
-                       return result);
+       vega20_populate_umdpstate_clocks(hwmgr);
 
        result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetPptLimit,
                        POWER_SOURCE_AC << 16, &hwmgr->default_power_limit);