Merge drm/drm-next into drm-misc-next

[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / pm / powerplay / hwmgr / vega12_hwmgr.c

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
index c73693dc4c09751fead5d9fa4dffaef61d8dcc5d..e9db137cd1c6cb79abb6894c03077ddd4f5a2fb9 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
@@ -1025,6 +1025,25 @@ static int vega12_get_all_clock_ranges(struct pp_hwmgr *hwmgr)
        return 0;
 }
 
+static void vega12_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+       struct vega12_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
+       struct vega12_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
+
+       if (gfx_dpm_table->count > VEGA12_UMD_PSTATE_GFXCLK_LEVEL &&
+           mem_dpm_table->count > VEGA12_UMD_PSTATE_MCLK_LEVEL) {
+               hwmgr->pstate_sclk = gfx_dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
+               hwmgr->pstate_mclk = mem_dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
+       } else {
+               hwmgr->pstate_sclk = gfx_dpm_table->dpm_levels[0].value;
+               hwmgr->pstate_mclk = mem_dpm_table->dpm_levels[0].value;
+       }
+
+       hwmgr->pstate_sclk_peak = gfx_dpm_table->dpm_levels[gfx_dpm_table->count].value;
+       hwmgr->pstate_mclk_peak = mem_dpm_table->dpm_levels[mem_dpm_table->count].value;
+}
+
 static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 {
        int tmp_result, result = 0;
@@ -1076,6 +1095,9 @@ static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
        PP_ASSERT_WITH_CODE(!result,
                        "Failed to setup default DPM tables!",
                        return result);
+
+       vega12_populate_umdpstate_clocks(hwmgr);
+
        return result;
 }