Merge tag 'amd-drm-next-5.20-2022-07-14' of https://gitlab.freedesktop.org/agd5f...

[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / display / dc / inc / dc_link_dp.h

diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
index b44c7b43f7db2175dbb0cea9ceec43341ccbbb6e..6682d9e181c6e328c6343bb61c173cbc38ef3e74 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
@@ -148,12 +148,12 @@ bool dp_is_max_vs_reached(
 void dp_hw_to_dpcd_lane_settings(
        const struct link_training_settings *lt_settings,
        const struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
-       union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX]);
+       union dpcd_training_lane dpcd_lane_settings[]);
 void dp_decide_lane_settings(
        const struct link_training_settings *lt_settings,
        const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
        struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
-       union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX]);
+       union dpcd_training_lane dpcd_lane_settings[]);
 
 uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval);