drm/amd/display: Avoid setting pixel rate divider to N/A

[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / display / dc / dcn32 / dcn32_hwseq.c

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index ac41a763bb1d1af167b0cdd4acb8b6add98a1bf4..d0b46a3e01551a4a93819f5011a463af47ef0222 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -1171,10 +1171,8 @@ unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsign
        two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);
        odm_combine_factor = get_odm_config(pipe_ctx, NULL);
 
        two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);
        odm_combine_factor = get_odm_config(pipe_ctx, NULL);
 

-       if (pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
-               return odm_combine_factor;
-

        if (is_dp_128b_132b_signal(pipe_ctx)) {
        if (is_dp_128b_132b_signal(pipe_ctx)) {

+               *k1_div = PIXEL_RATE_DIV_BY_1;

                *k2_div = PIXEL_RATE_DIV_BY_1;
        } else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) {
                *k1_div = PIXEL_RATE_DIV_BY_1;
                *k2_div = PIXEL_RATE_DIV_BY_1;
        } else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) {
                *k1_div = PIXEL_RATE_DIV_BY_1;