Merge tag 'amd-drm-next-5.20-2022-07-14' of https://gitlab.freedesktop.org/agd5f...

[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / display / dc / core / dc_link_dp.c

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index d380b8bc6f3952ce15d5b432b2cbff61b6985d23..dfc74aea2852a36cf11e46572f78d5ba86b3a321 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -695,7 +695,7 @@ bool dp_is_interlane_aligned(union lane_align_status_updated align_status)
 void dp_hw_to_dpcd_lane_settings(
                const struct link_training_settings *lt_settings,
                const struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
-               union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX])
+               union dpcd_training_lane dpcd_lane_settings[])
 {
        uint8_t lane = 0;
 
@@ -725,7 +725,7 @@ void dp_decide_lane_settings(
                const struct link_training_settings *lt_settings,
                const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
                struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
-               union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX])
+               union dpcd_training_lane dpcd_lane_settings[])
 {
        uint32_t lane;