Merge tag 'amd-drm-next-6.1-2022-09-08' of https://gitlab.freedesktop.org/agd5f/linux...

[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm_helpers.c

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 7fa36ff42c0d72e19d0194806198b55a347f9276..b8077fcd4651e1dfeca417041f30c1b5d5f3ac81 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -691,8 +691,14 @@ bool dm_helpers_dp_write_dsc_enable(
                const struct dc_stream_state *stream,
                bool enable)
 {
-       uint8_t enable_dsc = enable ? 1 : 0;
+       static const uint8_t DSC_DISABLE;
+       static const uint8_t DSC_DECODING = 0x01;
+       static const uint8_t DSC_PASSTHROUGH = 0x02;
+
        struct amdgpu_dm_connector *aconnector;
+       struct drm_dp_mst_port *port;
+       uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE;
+       uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE;
        uint8_t ret = 0;
 
        if (!stream)
@@ -712,8 +718,39 @@ bool dm_helpers_dp_write_dsc_enable(
                                aconnector->dsc_aux, stream, enable_dsc);
 #endif
 
-               ret = drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1);
-               DC_LOG_DC("Send DSC %s to MST RX\n", enable_dsc ? "enable" : "disable");
+               port = aconnector->port;
+
+               if (enable) {
+                       if (port->passthrough_aux) {
+                               ret = drm_dp_dpcd_write(port->passthrough_aux,
+                                                       DP_DSC_ENABLE,
+                                                       &enable_passthrough, 1);
+                               DC_LOG_DC("Sent DSC pass-through enable to virtual dpcd port, ret = %u\n",
+                                         ret);
+                       }
+
+                       ret = drm_dp_dpcd_write(aconnector->dsc_aux,
+                                               DP_DSC_ENABLE, &enable_dsc, 1);
+                       DC_LOG_DC("Sent DSC decoding enable to %s port, ret = %u\n",
+                                 (port->passthrough_aux) ? "remote RX" :
+                                 "virtual dpcd",
+                                 ret);
+               } else {
+                       ret = drm_dp_dpcd_write(aconnector->dsc_aux,
+                                               DP_DSC_ENABLE, &enable_dsc, 1);
+                       DC_LOG_DC("Sent DSC decoding disable to %s port, ret = %u\n",
+                                 (port->passthrough_aux) ? "remote RX" :
+                                 "virtual dpcd",
+                                 ret);
+
+                       if (port->passthrough_aux) {
+                               ret = drm_dp_dpcd_write(port->passthrough_aux,
+                                                       DP_DSC_ENABLE,
+                                                       &enable_passthrough, 1);
+                               DC_LOG_DC("Sent DSC pass-through disable to virtual dpcd port, ret = %u\n",
+                                         ret);
+                       }
+               }
        }
 
        if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) {
@@ -730,7 +767,7 @@ bool dm_helpers_dp_write_dsc_enable(
 #endif
        }
 
-       return (ret > 0);
+       return ret;
 }
 
 bool dm_helpers_is_dp_sink_present(struct dc_link *link)
@@ -841,6 +878,25 @@ void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigne
        //amdgpu_device_gpu_recover(dc_context->driver-context, NULL);
 }
 
+void dm_helpers_init_panel_settings(
+       struct dc_context *ctx,
+       struct dc_panel_config *panel_config)
+{
+       // Feature DSC
+       panel_config->dsc.disable_dsc_edp = false;
+       panel_config->dsc.force_dsc_edp_policy = 0;
+}
+
+void dm_helpers_override_panel_settings(
+       struct dc_context *ctx,
+       struct dc_panel_config *panel_config)
+{
+       // Feature DSC
+       if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
+               panel_config->dsc.disable_dsc_edp = true;
+       }
+}
+
 void *dm_helpers_allocate_gpu_mem(
                struct dc_context *ctx,
                enum dc_gpu_mem_alloc_type type,