Merge tag 'amd-drm-next-5.20-2022-07-14' of https://gitlab.freedesktop.org/agd5f...

[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index c03f300851fad8e8c36b960f919f6ca418bfe61c..3e83fed540e889bd2576552e50cea2838fa7568f 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -79,11 +79,13 @@
 #include <drm/drm_atomic.h>
 #include <drm/drm_atomic_uapi.h>
 #include <drm/drm_atomic_helper.h>
+#include <drm/drm_blend.h>
 #include <drm/drm_fb_helper.h>
 #include <drm/drm_fourcc.h>
 #include <drm/drm_edid.h>
 #include <drm/drm_vblank.h>
 #include <drm/drm_audio_component.h>
+#include <drm/drm_gem_atomic_helper.h>
 
 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
 
@@ -6874,7 +6876,7 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
        return &state->base;
 }
 
-#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
+#ifdef CONFIG_DEBUG_FS
 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
 {
        crtc_debugfs_init(crtc);
@@ -6975,7 +6977,7 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
        .enable_vblank = dm_enable_vblank,
        .disable_vblank = dm_disable_vblank,
        .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
-#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
+#if defined(CONFIG_DEBUG_FS)
        .late_register = amdgpu_dm_crtc_late_register,
 #endif
 };
@@ -7880,6 +7882,10 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
                goto error_unpin;
        }
 
+       r = drm_gem_plane_helper_prepare_fb(plane, new_state);
+       if (unlikely(r != 0))
+               goto error_unpin;
+
        amdgpu_bo_unreserve(rbo);
 
        afb->address = amdgpu_bo_gpu_offset(rbo);
@@ -9412,9 +9418,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
        struct dm_crtc_state *dm_old_crtc_state =
                        to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
        int planes_count = 0, vpos, hpos;
-       long r;
        unsigned long flags;
-       struct amdgpu_bo *abo;
        uint32_t target_vblank, last_flip_vblank;
        bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
        bool cursor_update = false;
@@ -9492,19 +9496,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
                        continue;
                }
 
-               abo = gem_to_amdgpu_bo(fb->obj[0]);
-
-               /*
-                * Wait for all fences on this FB. Do limited wait to avoid
-                * deadlock during GPU reset when this fence will not signal
-                * but we hold reservation lock for the BO.
-                */
-               r = dma_resv_wait_timeout(abo->tbo.base.resv,
-                                         DMA_RESV_USAGE_WRITE, false,
-                                         msecs_to_jiffies(5000));
-               if (unlikely(r <= 0))
-                       DRM_ERROR("Waiting for fences timed out!");
-
                fill_dc_plane_info_and_addr(
                        dm->adev, new_plane_state,
                        afb->tiling_flags,
@@ -9872,9 +9863,14 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
        struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
        int crtc_disable_count = 0;
        bool mode_set_reset_required = false;
+       int r;
 
        trace_amdgpu_dm_atomic_commit_tail_begin(state);
 
+       r = drm_atomic_helper_wait_for_fences(dev, state, false);
+       if (unlikely(r))
+               DRM_ERROR("Waiting for fences timed out!");
+
        drm_atomic_helper_update_legacy_modeset_state(dev, state);
 
        dm_state = dm_atomic_get_new_state(state);