drm/amdgpu: Initialize SPM_VMID with 0xf (v2)

[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / amdgpu / gfx_v8_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index e63f98b2d38974cdd2fbdd6f9251d92521c4d915..393a1324daa9326d5bf07c69b974c1ba9dd32ff2 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1318,6 +1318,10 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
                        return r;
        }
 
+       /* init spm vmid with 0xf */
+       if (adev->gfx.rlc.funcs->update_spm_vmid)
+               adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
+
        return 0;
 }
 
@@ -5594,6 +5598,18 @@ static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev)
        }
 }
 
+static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
+{
+       u32 data;
+
+       data = RREG32(mmRLC_SPM_VMID);
+
+       data &= ~RLC_SPM_VMID__RLC_SPM_VMID_MASK;
+       data |= (vmid & RLC_SPM_VMID__RLC_SPM_VMID_MASK) << RLC_SPM_VMID__RLC_SPM_VMID__SHIFT;
+
+       WREG32(mmRLC_SPM_VMID, data);
+}
+
 static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {
        .is_rlc_enabled = gfx_v8_0_is_rlc_enabled,
        .set_safe_mode = gfx_v8_0_set_safe_mode,
@@ -5605,7 +5621,8 @@ static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {
        .resume = gfx_v8_0_rlc_resume,
        .stop = gfx_v8_0_rlc_stop,
        .reset = gfx_v8_0_rlc_reset,
-       .start = gfx_v8_0_rlc_start
+       .start = gfx_v8_0_rlc_start,
+       .update_spm_vmid = gfx_v8_0_update_spm_vmid
 };
 
 static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,