Merge tag 'drm-misc-next-2020-06-26' of git://anongit.freedesktop.org/drm/drm-misc...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_vm_sdma.c
index 2a7a6f62d627e17c011b48ec8d327da6ac777523..f138e6aa4c2bf6f5f552e73bee53d2b4c5b48a7e 100644 (file)
@@ -61,10 +61,12 @@ static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p,
                                  struct dma_resv *resv,
                                  enum amdgpu_sync_mode sync_mode)
 {
+       enum amdgpu_ib_pool_type pool = p->immediate ? AMDGPU_IB_POOL_IMMEDIATE
+               : AMDGPU_IB_POOL_DELAYED;
        unsigned int ndw = AMDGPU_VM_SDMA_MIN_NUM_DW;
        int r;
 
-       r = amdgpu_job_alloc_with_ib(p->adev, ndw * 4, &p->job);
+       r = amdgpu_job_alloc_with_ib(p->adev, ndw * 4, pool, &p->job);
        if (r)
                return r;
 
@@ -90,11 +92,11 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p,
 {
        struct amdgpu_ib *ib = p->job->ibs;
        struct drm_sched_entity *entity;
-       struct dma_fence *f, *tmp;
        struct amdgpu_ring *ring;
+       struct dma_fence *f;
        int r;
 
-       entity = p->direct ? &p->vm->direct : &p->vm->delayed;
+       entity = p->immediate ? &p->vm->immediate : &p->vm->delayed;
        ring = container_of(entity->rq->sched, struct amdgpu_ring, sched);
 
        WARN_ON(ib->length_dw == 0);
@@ -104,15 +106,16 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p,
        if (r)
                goto error;
 
-       if (p->direct) {
-               tmp = dma_fence_get(f);
-               swap(p->vm->last_direct, tmp);
+       if (p->unlocked) {
+               struct dma_fence *tmp = dma_fence_get(f);
+
+               swap(p->vm->last_unlocked, f);
                dma_fence_put(tmp);
        } else {
-               dma_resv_add_shared_fence(p->vm->root.base.bo->tbo.base.resv, f);
+               amdgpu_bo_fence(p->vm->root.base.bo, f, true);
        }
 
-       if (fence && !p->direct)
+       if (fence && !p->immediate)
                swap(*fence, f);
        dma_fence_put(f);
        return 0;
@@ -142,7 +145,7 @@ static void amdgpu_vm_sdma_copy_ptes(struct amdgpu_vm_update_params *p,
        src += p->num_dw_left * 4;
 
        pe += amdgpu_bo_gpu_offset_no_check(bo);
-       trace_amdgpu_vm_copy_ptes(pe, src, count, p->direct);
+       trace_amdgpu_vm_copy_ptes(pe, src, count, p->immediate);
 
        amdgpu_vm_copy_pte(p->adev, ib, pe, src, count);
 }
@@ -169,7 +172,7 @@ static void amdgpu_vm_sdma_set_ptes(struct amdgpu_vm_update_params *p,
        struct amdgpu_ib *ib = p->job->ibs;
 
        pe += amdgpu_bo_gpu_offset_no_check(bo);
-       trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->direct);
+       trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->immediate);
        if (count < 3) {
                amdgpu_vm_write_pte(p->adev, ib, pe, addr | flags,
                                    count, incr);
@@ -198,6 +201,8 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p,
                                 uint64_t addr, unsigned count, uint32_t incr,
                                 uint64_t flags)
 {
+       enum amdgpu_ib_pool_type pool = p->immediate ? AMDGPU_IB_POOL_IMMEDIATE
+               : AMDGPU_IB_POOL_DELAYED;
        unsigned int i, ndw, nptes;
        uint64_t *pte;
        int r;
@@ -223,7 +228,8 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p,
                        ndw = max(ndw, AMDGPU_VM_SDMA_MIN_NUM_DW);
                        ndw = min(ndw, AMDGPU_VM_SDMA_MAX_NUM_DW);
 
-                       r = amdgpu_job_alloc_with_ib(p->adev, ndw * 4, &p->job);
+                       r = amdgpu_job_alloc_with_ib(p->adev, ndw * 4, pool,
+                                                    &p->job);
                        if (r)
                                return r;