drm/amd/powerplay: drop unused APIs and parameters
[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_pm.c
index d2401379bd33ee8a1acf63bc63f8cb0dc54965ca..20f39aa04fb9f661d36284526a06009096a1bd75 100644 (file)
@@ -1105,7 +1105,7 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
        }
 
        if (is_support_sw_smu(adev))
-               ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask, true);
+               ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask);
        else if (adev->powerplay.pp_funcs->force_clock_level)
                ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 
@@ -1173,7 +1173,7 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
        }
 
        if (is_support_sw_smu(adev))
-               ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask, true);
+               ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask);
        else if (adev->powerplay.pp_funcs->force_clock_level)
                ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 
@@ -1241,7 +1241,7 @@ static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
        }
 
        if (is_support_sw_smu(adev))
-               ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask, true);
+               ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask);
        else if (adev->powerplay.pp_funcs->force_clock_level)
                ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
        else
@@ -1311,7 +1311,7 @@ static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
        }
 
        if (is_support_sw_smu(adev))
-               ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask, true);
+               ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask);
        else if (adev->powerplay.pp_funcs->force_clock_level)
                ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
        else
@@ -1381,7 +1381,7 @@ static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
        }
 
        if (is_support_sw_smu(adev))
-               ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask, true);
+               ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask);
        else if (adev->powerplay.pp_funcs->force_clock_level)
                ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
        else
@@ -1451,7 +1451,7 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
        }
 
        if (is_support_sw_smu(adev))
-               ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask, true);
+               ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask);
        else if (adev->powerplay.pp_funcs->force_clock_level)
                ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
        else