Merge branches 'edac-spr', 'edac-igen6' and 'edac-misc' into edac-updates-for-v5.11

[sfrench/cifs-2.6.git] / drivers / edac / Kconfig

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index fa0c3b5797e4b966c99b5f67fa82f4375adcf90f..81c42664f21baf889e2c7f72cc0c142671595e73 100644 (file)
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -292,13 +292,6 @@ config EDAC_LAYERSCAPE
          Support for error detection and correction on Freescale memory
          controllers on Layerscape SoCs.
 
-config EDAC_MV64X60
-       tristate "Marvell MV64x60"
-       depends on MV64X60
-       help
-         Support for error detection and correction on the Marvell
-         MV64360 and MV64460 chipsets.
-
 config EDAC_PASEMI
        tristate "PA Semi PWRficient"
        depends on PPC_PASEMI && PCI
@@ -524,10 +517,10 @@ config EDAC_QCOM
          health, you should probably say 'Y' here.
 
 config EDAC_ASPEED
-       tristate "Aspeed AST 2500 SoC"
-       depends on MACH_ASPEED_G5
+       tristate "Aspeed AST BMC SoC"
+       depends on ARCH_ASPEED
        help
-         Support for error detection and correction on the Aspeed AST 2500 SoC.
+         Support for error detection and correction on the Aspeed AST BMC SoC.
 
          First, ECC must be configured in the bootloader. Then, this driver
          will expose error counters via the EDAC kernel framework.