x86, mce: clean up p6.c

[sfrench/cifs-2.6.git] / arch / x86 / kernel / cpu / mcheck / p6.c

diff --git a/arch/x86/kernel/cpu/mcheck/p6.c b/arch/x86/kernel/cpu/mcheck/p6.c
index 2ac52d7b434bd2b56543295e8bb326faa65493d7..43c24e667457f2b8598da9984bb59cde18aa00c4 100644 (file)
--- a/arch/x86/kernel/cpu/mcheck/p6.c
+++ b/arch/x86/kernel/cpu/mcheck/p6.c
@@ -2,11 +2,10 @@
  * P6 specific Machine Check Exception Reporting
  * (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>
  */
-
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
 #include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
 #include <linux/smp.h>
 
 #include <asm/processor.h>
@@ -18,9 +17,9 @@
 /* Machine Check Handler For PII/PIII */
 static void intel_machine_check(struct pt_regs *regs, long error_code)
 {
-       int recover = 1;
        u32 alow, ahigh, high, low;
        u32 mcgstl, mcgsth;
+       int recover = 1;
        int i;
 
        rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
@@ -35,12 +34,16 @@ static void intel_machine_check(struct pt_regs *regs, long error_code)
                if (high & (1<<31)) {
                        char misc[20];
                        char addr[24];
-                       misc[0] = addr[0] = '\0';
+
+                       misc[0] = '\0';
+                       addr[0] = '\0';
+
                        if (high & (1<<29))
                                recover |= 1;
                        if (high & (1<<25))
                                recover |= 2;
                        high &= ~(1<<31);
+
                        if (high & (1<<27)) {
                                rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
                                snprintf(misc, 20, "[%08x%08x]", ahigh, alow);
@@ -49,6 +52,7 @@ static void intel_machine_check(struct pt_regs *regs, long error_code)
                                rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
                                snprintf(addr, 24, " at %08x%08x", ahigh, alow);
                        }
+
                        printk(KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n",
                                smp_processor_id(), i, high, low, misc, addr);
                }
@@ -63,16 +67,17 @@ static void intel_machine_check(struct pt_regs *regs, long error_code)
        /*
         * Do not clear the MSR_IA32_MCi_STATUS if the error is not
         * recoverable/continuable.This will allow BIOS to look at the MSRs
-        * for errors if the OS could not log the error.
+        * for errors if the OS could not log the error:
         */
        for (i = 0; i < nr_mce_banks; i++) {
                unsigned int msr;
+
                msr = MSR_IA32_MC0_STATUS+i*4;
                rdmsr(msr, low, high);
                if (high & (1<<31)) {
-                       /* Clear it */
+                       /* Clear it: */
                        wrmsr(msr, 0UL, 0UL);
-                       /* Serialize */
+                       /* Serialize: */
                        wmb();
                        add_taint(TAINT_MACHINE_CHECK);
                }
@@ -81,7 +86,7 @@ static void intel_machine_check(struct pt_regs *regs, long error_code)
        wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
 }
 
-/* Set up machine check reporting for processors with Intel style MCE */
+/* Set up machine check reporting for processors with Intel style MCE: */
 void intel_p6_mcheck_init(struct cpuinfo_x86 *c)
 {
        u32 l, h;
@@ -97,6 +102,7 @@ void intel_p6_mcheck_init(struct cpuinfo_x86 *c)
 
        /* Ok machine check is available */
        machine_check_vector = intel_machine_check;
+       /* Make sure the vector pointer is visible before we enable MCEs: */
        wmb();
 
        printk(KERN_INFO "Intel machine check architecture supported.\n");