Merge tag 'x86_sev_for_v6.9_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git...

[sfrench/cifs-2.6.git] / arch / x86 / include / asm / msr-index.h

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index f8c73a549f0859320087848d27c69e79da3376ac..24c575cdd6b9fe240e563e63c191b7e1ab2e6909 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -36,8 +36,19 @@
 #define EFER_FFXSR             (1<<_EFER_FFXSR)
 #define EFER_AUTOIBRS          (1<<_EFER_AUTOIBRS)
 
-/* Intel MSRs. Some also available on other CPUs */
+/* FRED MSRs */
+#define MSR_IA32_FRED_RSP0     0x1cc                   /* Level 0 stack pointer */
+#define MSR_IA32_FRED_RSP1     0x1cd                   /* Level 1 stack pointer */
+#define MSR_IA32_FRED_RSP2     0x1ce                   /* Level 2 stack pointer */
+#define MSR_IA32_FRED_RSP3     0x1cf                   /* Level 3 stack pointer */
+#define MSR_IA32_FRED_STKLVLS  0x1d0                   /* Exception stack levels */
+#define MSR_IA32_FRED_SSP0     MSR_IA32_PL0_SSP        /* Level 0 shadow stack pointer */
+#define MSR_IA32_FRED_SSP1     0x1d1                   /* Level 1 shadow stack pointer */
+#define MSR_IA32_FRED_SSP2     0x1d2                   /* Level 2 shadow stack pointer */
+#define MSR_IA32_FRED_SSP3     0x1d3                   /* Level 3 shadow stack pointer */
+#define MSR_IA32_FRED_CONFIG   0x1d4                   /* Entrypoint and interrupt stack level */
 
+/* Intel MSRs. Some also available on other CPUs */
 #define MSR_TEST_CTRL                          0x00000033
 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT    29
 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT                BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)