RISC-V: Setup exception vector early

[sfrench/cifs-2.6.git] / arch / riscv / kernel / head.S

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 7ed1b22950fdba3b0f82d68c2330e9da00958b6b..d0c5c316e9bb12090fbbd9a8f39dcfc8b6d81b6a 100644 (file)
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -77,10 +77,16 @@ relocate:
        csrw CSR_SATP, a0
 .align 2
 1:
-       /* Set trap vector to spin forever to help debug */
-       la a0, .Lsecondary_park
+       /* Set trap vector to exception handler */
+       la a0, handle_exception
        csrw CSR_TVEC, a0
 
+       /*
+        * Set sup0 scratch register to 0, indicating to exception vector that
+        * we are presently executing in kernel.
+        */
+       csrw CSR_SCRATCH, zero
+
        /* Reload the global pointer */
 .option push
 .option norelax