riscv: fix scratch register clearing in M-mode.

[sfrench/cifs-2.6.git] / arch / riscv / kernel / head.S

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 84a6f0a4b120b4c8dbc0d171d9472fd17c862797..797802c73dee2ea673402745e791f3c1a7e13d21 100644 (file)
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -246,7 +246,7 @@ ENTRY(reset_regs)
        li      t4, 0
        li      t5, 0
        li      t6, 0
-       csrw    sscratch, 0
+       csrw    CSR_SCRATCH, 0
 
 #ifdef CONFIG_FPU
        csrr    t0, CSR_MISA