powerpc/mm: Update tlbiel loop on POWER10

[sfrench/cifs-2.6.git] / arch / powerpc / kvm / book3s_hv_builtin.c

diff --git a/arch/powerpc/kvm/book3s_hv_builtin.c b/arch/powerpc/kvm/book3s_hv_builtin.c
index 8f58dd20b362a9cb4727b8b7bb9eb97621ca189f..8053efdf7ea7318d94090fd9ada784fb3208b5e9 100644 (file)
--- a/arch/powerpc/kvm/book3s_hv_builtin.c
+++ b/arch/powerpc/kvm/book3s_hv_builtin.c
@@ -694,6 +694,7 @@ static void wait_for_sync(struct kvm_split_mode *sip, int phase)
 
 void kvmhv_p9_set_lpcr(struct kvm_split_mode *sip)
 {
+       int num_sets;
        unsigned long rb, set;
 
        /* wait for every other thread to get to real mode */
@@ -704,11 +705,19 @@ void kvmhv_p9_set_lpcr(struct kvm_split_mode *sip)
        mtspr(SPRN_LPID, sip->lpidr_req);
        isync();
 
+       /*
+        * P10 will flush all the congruence class with a single tlbiel
+        */
+       if (cpu_has_feature(CPU_FTR_ARCH_31))
+               num_sets =  1;
+       else
+               num_sets = POWER9_TLB_SETS_RADIX;
+
        /* Invalidate the TLB on thread 0 */
        if (local_paca->kvm_hstate.tid == 0) {
                sip->do_set = 0;
                asm volatile("ptesync" : : : "memory");
-               for (set = 0; set < POWER9_TLB_SETS_RADIX; ++set) {
+               for (set = 0; set < num_sets; ++set) {
                        rb = TLBIEL_INVAL_SET_LPID +
                                (set << TLBIEL_INVAL_SET_SHIFT);
                        asm volatile(PPC_TLBIEL(%0, %1, 0, 0, 0) : :