MIPS: Ingenic: Disable HPTLB for D0 XBurst CPUs too

[sfrench/cifs-2.6.git] / arch / mips / kernel / cpu-probe.c

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index e6853697a056118eaf293f92a7a0d1e5e3550ffb..31cb9199197ca1049c87e77784006c15c12b923e 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1830,16 +1830,17 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
                 */
                case PRID_COMP_INGENIC_D0:
                        c->isa_level &= ~MIPS_CPU_ISA_M32R2;
-                       break;
+                       fallthrough;
 
                /*
                 * The config0 register in the XBurst CPUs with a processor ID of
-                * PRID_COMP_INGENIC_D1 has an abandoned huge page tlb mode, this
-                * mode is not compatible with the MIPS standard, it will cause
-                * tlbmiss and into an infinite loop (line 21 in the tlb-funcs.S)
-                * when starting the init process. After chip reset, the default
-                * is HPTLB mode, Write 0xa9000000 to cp0 register 5 sel 4 to
-                * switch back to VTLB mode to prevent getting stuck.
+                * PRID_COMP_INGENIC_D0 or PRID_COMP_INGENIC_D1 has an abandoned
+                * huge page tlb mode, this mode is not compatible with the MIPS
+                * standard, it will cause tlbmiss and into an infinite loop
+                * (line 21 in the tlb-funcs.S) when starting the init process.
+                * After chip reset, the default is HPTLB mode, Write 0xa9000000
+                * to cp0 register 5 sel 4 to switch back to VTLB mode to prevent
+                * getting stuck.
                 */
                case PRID_COMP_INGENIC_D1:
                        write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS);