MIPS: Fix CP0 counter erratum detection for R4k CPUs

[sfrench/cifs-2.6.git] / arch / mips / include / asm / timex.h

diff --git a/arch/mips/include/asm/timex.h b/arch/mips/include/asm/timex.h
index b05bb70a2e46f3d1af2d60421e6b81644e1f29ce..8026baf46e729262065571c785635bd6ed876795 100644 (file)
--- a/arch/mips/include/asm/timex.h
+++ b/arch/mips/include/asm/timex.h
@@ -40,9 +40,9 @@
 typedef unsigned int cycles_t;
 
 /*
- * On R4000/R4400 before version 5.0 an erratum exists such that if the
- * cycle counter is read in the exact moment that it is matching the
- * compare register, no interrupt will be generated.
+ * On R4000/R4400 an erratum exists such that if the cycle counter is
+ * read in the exact moment that it is matching the compare register,
+ * no interrupt will be generated.
  *
  * There is a suggested workaround and also the erratum can't strike if
  * the compare interrupt isn't being used as the clock source device.
@@ -63,7 +63,7 @@ static inline int can_use_mips_counter(unsigned int prid)
        if (!__builtin_constant_p(cpu_has_counter))
                asm volatile("" : "=m" (cpu_data[0].options));
        if (likely(cpu_has_counter &&
-                  prid >= (PRID_IMP_R4000 | PRID_REV_ENCODE_44(5, 0))))
+                  prid > (PRID_IMP_R4000 | PRID_REV_ENCODE_44(15, 15))))
                return 1;
        else
                return 0;