Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

[sfrench/cifs-2.6.git] / arch / arm64 / include / asm / sysreg.h

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index bae9eeae99750c137b29be32c84706cb7e7da2d8..b481935e9314e5e13fa5543597d2b34558844c47 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -140,25 +140,17 @@
 #define SYS_SVCR_SMSTART_SM_EL0                sys_reg(0, 3, 4, 3, 3)
 #define SYS_SVCR_SMSTOP_SMZA_EL0       sys_reg(0, 3, 4, 6, 3)
 
-#define SYS_OSDTRRX_EL1                        sys_reg(2, 0, 0, 0, 2)
-#define SYS_MDCCINT_EL1                        sys_reg(2, 0, 0, 2, 0)
-#define SYS_MDSCR_EL1                  sys_reg(2, 0, 0, 2, 2)
-#define SYS_OSDTRTX_EL1                        sys_reg(2, 0, 0, 3, 2)
-#define SYS_OSECCR_EL1                 sys_reg(2, 0, 0, 6, 2)
 #define SYS_DBGBVRn_EL1(n)             sys_reg(2, 0, 0, n, 4)
 #define SYS_DBGBCRn_EL1(n)             sys_reg(2, 0, 0, n, 5)
 #define SYS_DBGWVRn_EL1(n)             sys_reg(2, 0, 0, n, 6)
 #define SYS_DBGWCRn_EL1(n)             sys_reg(2, 0, 0, n, 7)
 #define SYS_MDRAR_EL1                  sys_reg(2, 0, 1, 0, 0)
 
-#define SYS_OSLAR_EL1                  sys_reg(2, 0, 1, 0, 4)
-#define SYS_OSLAR_OSLK                 BIT(0)
-
 #define SYS_OSLSR_EL1                  sys_reg(2, 0, 1, 1, 4)
-#define SYS_OSLSR_OSLM_MASK            (BIT(3) | BIT(0))
-#define SYS_OSLSR_OSLM_NI              0
-#define SYS_OSLSR_OSLM_IMPLEMENTED     BIT(3)
-#define SYS_OSLSR_OSLK                 BIT(1)
+#define OSLSR_EL1_OSLM_MASK            (BIT(3) | BIT(0))
+#define OSLSR_EL1_OSLM_NI              0
+#define OSLSR_EL1_OSLM_IMPLEMENTED     BIT(3)
+#define OSLSR_EL1_OSLK                 BIT(1)
 
 #define SYS_OSDLR_EL1                  sys_reg(2, 0, 1, 3, 4)
 #define SYS_DBGPRCR_EL1                        sys_reg(2, 0, 1, 4, 4)
@@ -241,54 +233,8 @@
 
 /*** End of Statistical Profiling Extension ***/
 
-/*
- * TRBE Registers
- */
-#define SYS_TRBLIMITR_EL1              sys_reg(3, 0, 9, 11, 0)
-#define SYS_TRBPTR_EL1                 sys_reg(3, 0, 9, 11, 1)
-#define SYS_TRBBASER_EL1               sys_reg(3, 0, 9, 11, 2)
-#define SYS_TRBSR_EL1                  sys_reg(3, 0, 9, 11, 3)
-#define SYS_TRBMAR_EL1                 sys_reg(3, 0, 9, 11, 4)
-#define SYS_TRBTRG_EL1                 sys_reg(3, 0, 9, 11, 6)
-#define SYS_TRBIDR_EL1                 sys_reg(3, 0, 9, 11, 7)
-
-#define TRBLIMITR_LIMIT_MASK           GENMASK_ULL(51, 0)
-#define TRBLIMITR_LIMIT_SHIFT          12
-#define TRBLIMITR_NVM                  BIT(5)
-#define TRBLIMITR_TRIG_MODE_MASK       GENMASK(1, 0)
-#define TRBLIMITR_TRIG_MODE_SHIFT      3
-#define TRBLIMITR_FILL_MODE_MASK       GENMASK(1, 0)
-#define TRBLIMITR_FILL_MODE_SHIFT      1
-#define TRBLIMITR_ENABLE               BIT(0)
-#define TRBPTR_PTR_MASK                        GENMASK_ULL(63, 0)
-#define TRBPTR_PTR_SHIFT               0
-#define TRBBASER_BASE_MASK             GENMASK_ULL(51, 0)
-#define TRBBASER_BASE_SHIFT            12
-#define TRBSR_EC_MASK                  GENMASK(5, 0)
-#define TRBSR_EC_SHIFT                 26
-#define TRBSR_IRQ                      BIT(22)
-#define TRBSR_TRG                      BIT(21)
-#define TRBSR_WRAP                     BIT(20)
-#define TRBSR_ABORT                    BIT(18)
-#define TRBSR_STOP                     BIT(17)
-#define TRBSR_MSS_MASK                 GENMASK(15, 0)
-#define TRBSR_MSS_SHIFT                        0
-#define TRBSR_BSC_MASK                 GENMASK(5, 0)
-#define TRBSR_BSC_SHIFT                        0
-#define TRBSR_FSC_MASK                 GENMASK(5, 0)
-#define TRBSR_FSC_SHIFT                        0
-#define TRBMAR_SHARE_MASK              GENMASK(1, 0)
-#define TRBMAR_SHARE_SHIFT             8
-#define TRBMAR_OUTER_MASK              GENMASK(3, 0)
-#define TRBMAR_OUTER_SHIFT             4
-#define TRBMAR_INNER_MASK              GENMASK(3, 0)
-#define TRBMAR_INNER_SHIFT             0
-#define TRBTRG_TRG_MASK                        GENMASK(31, 0)
-#define TRBTRG_TRG_SHIFT               0
-#define TRBIDR_FLAG                    BIT(5)
-#define TRBIDR_PROG                    BIT(4)
-#define TRBIDR_ALIGN_MASK              GENMASK(3, 0)
-#define TRBIDR_ALIGN_SHIFT             0
+#define TRBSR_EL1_BSC_MASK             GENMASK(5, 0)
+#define TRBSR_EL1_BSC_SHIFT            0
 
 #define SYS_PMINTENSET_EL1             sys_reg(3, 0, 9, 14, 1)
 #define SYS_PMINTENCLR_EL1             sys_reg(3, 0, 9, 14, 2)
@@ -765,6 +711,25 @@
 #define ICH_VTR_TDS_SHIFT      19
 #define ICH_VTR_TDS_MASK       (1 << ICH_VTR_TDS_SHIFT)
 
+/*
+ * Permission Indirection Extension (PIE) permission encodings.
+ * Encodings with the _O suffix, have overlays applied (Permission Overlay Extension).
+ */
+#define PIE_NONE_O     0x0
+#define PIE_R_O                0x1
+#define PIE_X_O                0x2
+#define PIE_RX_O       0x3
+#define PIE_RW_O       0x5
+#define PIE_RWnX_O     0x6
+#define PIE_RWX_O      0x7
+#define PIE_R          0x8
+#define PIE_GCS                0x9
+#define PIE_RX         0xa
+#define PIE_RW         0xc
+#define PIE_RWX                0xe
+
+#define PIRx_ELx_PERM(idx, perm)       ((perm) << ((idx) * 4))
+
 #define ARM64_FEATURE_FIELD_BITS       4
 
 /* Defined for compatibility only, do not add new users. */