arm64: dts: qcom: sc7180: Add UFS nodes

[sfrench/cifs-2.6.git] / arch / arm64 / boot / dts / qcom / sc7180.dtsi

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 1fffd5fc7812ea5f45237c26657d3eb5c5958351..ed2e54988dafc57b0b4270852fdbd3053b02cc78 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -1532,6 +1532,76 @@
                        qcom,bcm-voters = <&apps_bcm_voter>;
                };
 
+               ufs_mem_hc: ufshc@1d84000 {
+                       compatible = "qcom,sc7180-ufshc", "qcom,ufshc",
+                                    "jedec,ufs-2.0";
+                       reg = <0 0x01d84000 0 0x3000>;
+                       interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+                       phys = <&ufs_mem_phy>;
+                       phy-names = "ufsphy";
+                       lanes-per-direction = <1>;
+                       #reset-cells = <1>;
+                       resets = <&gcc GCC_UFS_PHY_BCR>;
+                       reset-names = "rst";
+
+                       power-domains = <&gcc UFS_PHY_GDSC>;
+
+                       iommus = <&apps_smmu 0xa0 0x0>;
+
+                       clock-names = "core_clk",
+                                     "bus_aggr_clk",
+                                     "iface_clk",
+                                     "core_clk_unipro",
+                                     "ref_clk",
+                                     "tx_lane0_sync_clk",
+                                     "rx_lane0_sync_clk";
+                       clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+                                <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+                                <&gcc GCC_UFS_PHY_AHB_CLK>,
+                                <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+                                <&rpmhcc RPMH_CXO_CLK>,
+                                <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+                                <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
+                       freq-table-hz = <50000000 200000000>,
+                                       <0 0>,
+                                       <0 0>,
+                                       <37500000 150000000>,
+                                       <0 0>,
+                                       <0 0>,
+                                       <0 0>;
+
+                       interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+                                       <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+                                        &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
+                       interconnect-names = "ufs-ddr", "cpu-ufs";
+
+                       qcom,ice = <&ice>;
+
+                       status = "disabled";
+               };
+
+               ufs_mem_phy: phy@1d87000 {
+                       compatible = "qcom,sc7180-qmp-ufs-phy",
+                                    "qcom,sm7150-qmp-ufs-phy";
+                       reg = <0 0x01d87000 0 0x1000>;
+                       clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
+                                <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+                       clock-names = "ref", "ref_aux";
+                       power-domains = <&gcc UFS_PHY_GDSC>;
+                       resets = <&ufs_mem_hc 0>;
+                       reset-names = "ufsphy";
+                       #phy-cells = <0>;
+                       status = "disabled";
+               };
+
+               ice: crypto@1d90000 {
+                       compatible = "qcom,sc7180-inline-crypto-engine",
+                                    "qcom,inline-crypto-engine";
+                       reg = <0 0x01d90000 0 0x8000>;
+                       clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+               };
+
                ipa: ipa@1e40000 {
                        compatible = "qcom,sc7180-ipa";