Merge tag 'dt-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

[sfrench/cifs-2.6.git] / arch / arm64 / boot / dts / freescale / imx8mm-kontron-n801x-s.dts

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts
index e99e7644ff392b1a92ad95f5749f6d4965802a3c..d40caf14ac4aa6375e0a85e63230b18b23b6025a 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts
@@ -123,8 +123,8 @@
 
                ethphy: ethernet-phy@0 {
                        reg = <0>;
-                       reset-assert-us = <100>;
-                       reset-deassert-us = <100>;
+                       reset-assert-us = <1>;
+                       reset-deassert-us = <15000>;
                        reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
                };
        };
@@ -191,8 +191,10 @@
 };
 
 &usdhc2 {
-       pinctrl-names = "default";
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
        pinctrl-0 = <&pinctrl_usdhc2>;
+       pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
        vmmc-supply = <&reg_vdd_3v3>;
        vqmmc-supply = <&reg_nvcc_sd>;
        cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
@@ -321,4 +323,28 @@
                        MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x019
                >;
        };
+
+       pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x194
+                       MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                 0x1d4
+                       MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0             0x1d4
+                       MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1             0x1d4
+                       MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d4
+                       MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d4
+                       MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x019
+               >;
+       };
+
+       pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x196
+                       MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                 0x1d6
+                       MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0             0x1d6
+                       MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1             0x1d6
+                       MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d6
+                       MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d6
+                       MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x019
+               >;
+       };
 };