ARM: 9030/1: entry: omit FP emulation for UND exceptions taken in kernel mode

[sfrench/cifs-2.6.git] / arch / arm / kernel / entry-armv.S

diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index c4220f51fcf3a3e022324d8afdf02cf22c9c9eef..0ea8529a48726208f2b79a072cb3c532548d36cb 100644 (file)
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -252,31 +252,10 @@ __und_svc:
 #else
        svc_entry
 #endif
-       @
-       @ call emulation code, which returns using r9 if it has emulated
-       @ the instruction, or the more conventional lr if we are to treat
-       @ this as a real undefined instruction
-       @
-       @  r0 - instruction
-       @
-#ifndef CONFIG_THUMB2_KERNEL
-       ldr     r0, [r4, #-4]
-#else
-       mov     r1, #2
-       ldrh    r0, [r4, #-2]                   @ Thumb instruction at LR - 2
-       cmp     r0, #0xe800                     @ 32-bit instruction if xx >= 0
-       blo     __und_svc_fault
-       ldrh    r9, [r4]                        @ bottom 16 bits
-       add     r4, r4, #2
-       str     r4, [sp, #S_PC]
-       orr     r0, r9, r0, lsl #16
-#endif
-       badr    r9, __und_svc_finish
-       mov     r2, r4
-       bl      call_fpe
 
        mov     r1, #4                          @ PC correction to apply
-__und_svc_fault:
+ THUMB(        tst     r5, #PSR_T_BIT          )       @ exception taken in Thumb mode?
+ THUMB(        movne   r1, #2                  )       @ if so, fix up PC correction
        mov     r0, sp                          @ struct pt_regs *regs
        bl      __und_fault