Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / s3c2416.dtsi

diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi
index 6adf64ea3ff29883eaaf667265363abcab385739..4f084f4fe44f054d7ea80d4afb4facd09092d91c 100644 (file)
--- a/arch/arm/boot/dts/s3c2416.dtsi
+++ b/arch/arm/boot/dts/s3c2416.dtsi
@@ -18,54 +18,22 @@
        };
 
        cpus {
-               cpu {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       device_type = "cpu";
                        compatible = "arm,arm926ej-s";
+                       reg = <0x0>;
                };
        };
 
-       interrupt-controller@4a000000 {
-               compatible = "samsung,s3c2416-irq";
-       };
-
        clocks: clock-controller@4c000000 {
                compatible = "samsung,s3c2416-clock";
                reg = <0x4c000000 0x40>;
                #clock-cells = <1>;
        };
 
-       pinctrl@56000000 {
-               compatible = "samsung,s3c2416-pinctrl";
-       };
-
-       timer@51000000 {
-               clocks = <&clocks PCLK_PWM>;
-               clock-names = "timers";
-       };
-
-       uart_0: serial@50000000 {
-               compatible = "samsung,s3c2440-uart";
-               clock-names = "uart", "clk_uart_baud2",
-                               "clk_uart_baud3";
-               clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
-                               <&clocks SCLK_UART>;
-       };
-
-       uart_1: serial@50004000 {
-               compatible = "samsung,s3c2440-uart";
-               clock-names = "uart", "clk_uart_baud2",
-                               "clk_uart_baud3";
-               clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
-                               <&clocks SCLK_UART>;
-       };
-
-       uart_2: serial@50008000 {
-               compatible = "samsung,s3c2440-uart";
-               clock-names = "uart", "clk_uart_baud2",
-                               "clk_uart_baud3";
-               clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
-                               <&clocks SCLK_UART>;
-       };
-
        uart_3: serial@5000c000 {
                compatible = "samsung,s3c2440-uart";
                reg = <0x5000C000 0x4000>;
@@ -98,22 +66,59 @@
                                <&clocks MUX_HSMMC1>;
                status = "disabled";
        };
+};
 
-       watchdog: watchdog@53000000 {
-               interrupts = <1 9 27 3>;
-               clocks = <&clocks PCLK_WDT>;
-               clock-names = "watchdog";
-       };
+&i2c {
+       compatible = "samsung,s3c2440-i2c";
+       clocks = <&clocks PCLK_I2C0>;
+       clock-names = "i2c";
+};
 
-       rtc: rtc@57000000 {
-               compatible = "samsung,s3c2416-rtc";
-               clocks = <&clocks PCLK_RTC>;
-               clock-names = "rtc";
-       };
+&intc {
+       compatible = "samsung,s3c2416-irq";
+};
 
-       i2c@54000000 {
-               compatible = "samsung,s3c2440-i2c";
-               clocks = <&clocks PCLK_I2C0>;
-               clock-names = "i2c";
-       };
+&pinctrl_0 {
+       compatible = "samsung,s3c2416-pinctrl";
+};
+
+&rtc {
+       compatible = "samsung,s3c2416-rtc";
+       clocks = <&clocks PCLK_RTC>;
+       clock-names = "rtc";
+};
+
+&timer {
+       clocks = <&clocks PCLK_PWM>;
+       clock-names = "timers";
+};
+
+&uart_0 {
+       compatible = "samsung,s3c2440-uart";
+       clock-names = "uart", "clk_uart_baud2",
+                       "clk_uart_baud3";
+       clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
+                       <&clocks SCLK_UART>;
+};
+
+&uart_1 {
+       compatible = "samsung,s3c2440-uart";
+       clock-names = "uart", "clk_uart_baud2",
+                       "clk_uart_baud3";
+       clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
+                       <&clocks SCLK_UART>;
+};
+
+&uart_2 {
+       compatible = "samsung,s3c2440-uart";
+       clock-names = "uart", "clk_uart_baud2",
+                       "clk_uart_baud3";
+       clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
+                       <&clocks SCLK_UART>;
+};
+
+&watchdog {
+       interrupts = <1 9 27 3>;
+       clocks = <&clocks PCLK_WDT>;
+       clock-names = "watchdog";
 };