ARM: dts: rockchip: fix PPI misconfiguration on Cortex-A9 socs

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / rk3xxx.dtsi

diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 233513cdd2793c3ba23790455a515ae6942698f5..c5b8592af73cae2a7a4e046321cb90621e92b32b 100644 (file)
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -132,14 +132,14 @@
        global_timer: global-timer@1013c200 {
                compatible = "arm,cortex-a9-global-timer";
                reg = <0x1013c200 0x20>;
-               interrupts = <GIC_PPI 11 0x304>;
+               interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
                clocks = <&cru CORE_PERI>;
        };
 
        local_timer: local-timer@1013c600 {
                compatible = "arm,cortex-a9-twd-timer";
                reg = <0x1013c600 0x20>;
-               interrupts = <GIC_PPI 13 0x304>;
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
                clocks = <&cru CORE_PERI>;
        };