Merge tag 'v5.5-rc3' into sched/core, to pick up fixes

[sfrench/cifs-2.6.git] / arch / arc / include / asm / mmu.h

diff --git a/arch/arc/include/asm/mmu.h b/arch/arc/include/asm/mmu.h
index 98cadf1a09acfd9a6d4b0ca4900140d4054cef6a..26b731d32a2b9ccd0d876ed43e61e8d1072be98c 100644 (file)
--- a/arch/arc/include/asm/mmu.h
+++ b/arch/arc/include/asm/mmu.h
@@ -40,6 +40,10 @@
 #define ARC_REG_SCRATCH_DATA0  0x46c
 #endif
 
+#if defined(CONFIG_ISA_ARCV2) || !defined(CONFIG_SMP)
+#define        ARC_USE_SCRATCH_REG
+#endif
+
 /* Bits in MMU PID register */
 #define __TLB_ENABLE           (1 << 31)
 #define __PROG_ENABLE          (1 << 30)
@@ -63,6 +67,8 @@
 #if (CONFIG_ARC_MMU_VER >= 2)
 #define TLBWriteNI  0x5                /* write JTLB without inv uTLBs */
 #define TLBIVUTLB   0x6                /* explicitly inv uTLBs */
+#else
+#define TLBWriteNI  TLBWrite   /* Not present in hardware, fallback */
 #endif
 
 #if (CONFIG_ARC_MMU_VER >= 4)