#define ERST_RANGE_NVRAM 0x0002
#define ERST_RANGE_SLOW 0x0004
+/* ERST Exec max timings */
+#define ERST_EXEC_TIMING_MAX_MASK 0xFFFFFFFF00000000
+#define ERST_EXEC_TIMING_MAX_SHIFT 32
+
/*
* ERST Error Log Address Range, used as buffer for reading/writing
* error records.
u64 size;
void __iomem *vaddr;
u32 attr;
+ u64 timings;
} erst_erange;
/*
}
}
+static inline u64 erst_get_timeout(void)
+{
+ u64 timeout = FIRMWARE_TIMEOUT;
+
+ if (erst_erange.attr & ERST_RANGE_SLOW) {
+ timeout = ((erst_erange.timings & ERST_EXEC_TIMING_MAX_MASK) >>
+ ERST_EXEC_TIMING_MAX_SHIFT) * NSEC_PER_MSEC;
+ if (timeout < FIRMWARE_TIMEOUT)
+ timeout = FIRMWARE_TIMEOUT;
+ }
+ return timeout;
+}
+
static int erst_timedout(u64 *t, u64 spin_unit)
{
if ((s64)*t < spin_unit) {
{
int rc;
u64 val;
- u64 timeout = FIRMWARE_TIMEOUT;
+ u64 timeout;
u64 stall_time;
+ timeout = erst_get_timeout();
+
if (ctx->var1 > FIRMWARE_MAX_STALL) {
if (!in_nmi())
pr_warn(FW_WARN
if (rc)
return rc;
range->attr = apei_exec_ctx_get_output(&ctx);
+ rc = apei_exec_run(&ctx, ACPI_ERST_EXECUTE_TIMINGS);
+ if (rc == 0)
+ range->timings = apei_exec_ctx_get_output(&ctx);
+ else if (rc == -ENOENT)
+ range->timings = 0;
+ else
+ return rc;
return 0;
}
static int __erst_write_to_storage(u64 offset)
{
struct apei_exec_context ctx;
- u64 timeout = FIRMWARE_TIMEOUT;
+ u64 timeout;
u64 val;
int rc;
+ timeout = erst_get_timeout();
+
erst_exec_ctx_init(&ctx);
rc = apei_exec_run_optional(&ctx, ACPI_ERST_BEGIN_WRITE);
if (rc)
static int __erst_read_from_storage(u64 record_id, u64 offset)
{
struct apei_exec_context ctx;
- u64 timeout = FIRMWARE_TIMEOUT;
+ u64 timeout;
u64 val;
int rc;
+ timeout = erst_get_timeout();
+
erst_exec_ctx_init(&ctx);
rc = apei_exec_run_optional(&ctx, ACPI_ERST_BEGIN_READ);
if (rc)
static int __erst_clear_from_storage(u64 record_id)
{
struct apei_exec_context ctx;
- u64 timeout = FIRMWARE_TIMEOUT;
+ u64 timeout;
u64 val;
int rc;
+ timeout = erst_get_timeout();
+
erst_exec_ctx_init(&ctx);
rc = apei_exec_run_optional(&ctx, ACPI_ERST_BEGIN_CLEAR);
if (rc)