clk: zynq: trivial warning fix
authorShubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Tue, 22 Feb 2022 13:09:02 +0000 (18:39 +0530)
committerStephen Boyd <sboyd@kernel.org>
Tue, 29 Mar 2022 17:17:42 +0000 (10:17 -0700)
Fix the below warning

WARNING: Missing a blank line after declarations
+               int enable = !!(fclk_enable & BIT(i - fclk0));
+               zynq_clk_register_fclk(i, clk_output_name[i],

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Link: https://lore.kernel.org/r/20220222130903.17235-2-shubhrajyoti.datta@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/zynq/clkc.c

index 204b83d911b902865fbd130d31a48512ea5a1ca8..434511dcf5cb240604d0c96b1c62046e1d730dc0 100644 (file)
@@ -349,6 +349,7 @@ static void __init zynq_clk_setup(struct device_node *np)
        /* Peripheral clocks */
        for (i = fclk0; i <= fclk3; i++) {
                int enable = !!(fclk_enable & BIT(i - fclk0));
+
                zynq_clk_register_fclk(i, clk_output_name[i],
                                SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
                                periph_parents, enable);