arm64: Add ID_DFR0_EL1.PerfMon values for PMUv3p7 and IMP_DEF

Align the ID_DFR0_EL1.PerfMon values with ID_AA64DFR0_EL1.PMUver.

Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20221113163832.3154370-2-maz@kernel.org

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 7d301700d1a9369216889c39c6577cdc11f2cec8..84f59ce1dc6dbde52bdb45cd1dc58527bf293f2e 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -698,6 +698,8 @@
 #define ID_DFR0_PERFMON_8_1            0x4
 #define ID_DFR0_PERFMON_8_4            0x5
 #define ID_DFR0_PERFMON_8_5            0x6
+#define ID_DFR0_PERFMON_8_7            0x7
+#define ID_DFR0_PERFMON_IMP_DEF                0xf
 
 #define ID_ISAR4_SWP_FRAC_SHIFT                28
 #define ID_ISAR4_PSR_M_SHIFT           24