drm/amd/display: Add primary tmz_c and meta tmz tmz_c.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 57c74ac65beb6563429758312c777c205596e11c..39b72f696ae9df5fdb78f78dba2b61e31cc37684 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -299,8 +299,9 @@ bool hubp1_program_surface_flip_and_addr(
                if (address->grph.addr.quad_part == 0)
                        break;
 
-               REG_UPDATE(DCSURF_SURFACE_CONTROL,
-                               PRIMARY_SURFACE_TMZ, address->tmz_surface);
+               REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
+                               PRIMARY_SURFACE_TMZ, address->tmz_surface,
+                               PRIMARY_META_SURFACE_TMZ, address->tmz_surface);
 
                if (address->grph.meta_addr.quad_part != 0) {
                        REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
@@ -325,8 +326,11 @@ bool hubp1_program_surface_flip_and_addr(
                        || address->video_progressive.chroma_addr.quad_part == 0)
                        break;
 
-               REG_UPDATE(DCSURF_SURFACE_CONTROL,
-                               PRIMARY_SURFACE_TMZ, address->tmz_surface);
+               REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
+                               PRIMARY_SURFACE_TMZ, address->tmz_surface,
+                               PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
+                               PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
+                               PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
 
                if (address->video_progressive.luma_meta_addr.quad_part != 0) {
                        REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
@@ -368,8 +372,11 @@ bool hubp1_program_surface_flip_and_addr(
                if (address->grph_stereo.right_addr.quad_part == 0)
                        break;
 
-               REG_UPDATE(DCSURF_SURFACE_CONTROL,
-                               PRIMARY_SURFACE_TMZ, address->tmz_surface);
+               REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
+                               PRIMARY_SURFACE_TMZ, address->tmz_surface,
+                               PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
+                               PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
+                               PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
 
                if (address->grph_stereo.right_meta_addr.quad_part != 0) {
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index a4bcb598588ff6a26609e3bd30d18876db55712a..4a3703e12ea1c6c5504d41725b6c57fd601dfd08 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -296,6 +296,9 @@
        HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\
        HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\
        HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\
+       HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ_C, mask_sh),\
+       HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ, mask_sh),\
+       HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ_C, mask_sh),\
        HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
        HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
        HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
@@ -457,6 +460,13 @@
        type SURFACE_EARLIEST_INUSE_ADDRESS_C;\
        type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C;\
        type PRIMARY_SURFACE_TMZ;\
+       type PRIMARY_SURFACE_TMZ_C;\
+       type SECONDARY_SURFACE_TMZ;\
+       type SECONDARY_SURFACE_TMZ_C;\
+       type PRIMARY_META_SURFACE_TMZ;\
+       type PRIMARY_META_SURFACE_TMZ_C;\
+       type SECONDARY_META_SURFACE_TMZ;\
+       type SECONDARY_META_SURFACE_TMZ_C;\
        type PRIMARY_SURFACE_DCC_EN;\
        type PRIMARY_SURFACE_DCC_IND_64B_BLK;\
        type DET_BUF_PLANE1_BASE_ADDRESS;\