RDMA/mlx5: Add SQD2RTS bit to the alloc ucontext response
authorSergey Gorenko <sergeygo@nvidia.com>
Mon, 10 May 2021 10:23:33 +0000 (13:23 +0300)
committerJason Gunthorpe <jgg@nvidia.com>
Thu, 20 May 2021 14:41:07 +0000 (11:41 -0300)
The new bit in the comp_mask is needed to mark that kernel supports
SQD2RTS transition for the modify QP command.

Link: https://lore.kernel.org/r/7ce705fedac1b2b8e3a2f4013e04244dc5946344.1620641808.git.leonro@nvidia.com
Reviewed-by: Evgenii Kochetov <evgeniik@nvidia.com>
Signed-off-by: Sergey Gorenko <sergeygo@nvidia.com>
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
drivers/infiniband/hw/mlx5/main.c
include/uapi/rdma/mlx5-abi.h

index 6d1dd09a4388177be9a0fedae2c89d026ace1be4..312aa731860dee42794d0059643691d9fed3fa8a 100644 (file)
@@ -1817,6 +1817,10 @@ static int set_ucontext_resp(struct ib_ucontext *uctx,
                resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE;
 
        resp->num_dyn_bfregs = bfregi->num_dyn_bfregs;
+
+       if (MLX5_CAP_GEN(dev->mdev, drain_sigerr))
+               resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS;
+
        return 0;
 }
 
index 27905a0268c9f286f383f17af19b36bb8989727d..995faf8f44bd3fbdc8b6de3e7dad4dda1b15b5ea 100644 (file)
@@ -101,6 +101,7 @@ enum mlx5_ib_alloc_ucontext_resp_mask {
        MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
        MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY    = 1UL << 1,
        MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE               = 1UL << 2,
+       MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS           = 1UL << 3,
 };
 
 enum mlx5_user_cmds_supp_uhw {