clk: uniphier: add ethernet clock control support for PXs3

Add clock control for ethernet controller on PXs3 SoC.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index 06c5269f63f54968c5f9e808e5cd38d85b7d0bd3..fa7f2f3f8e36a5c3877b52f61f724b7d46990cca 100644 (file)
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -244,6 +244,8 @@ const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
        UNIPHIER_LD20_SYS_CLK_SD,
        UNIPHIER_LD11_SYS_CLK_NAND(2),
        UNIPHIER_LD11_SYS_CLK_EMMC(4),
+       UNIPHIER_CLK_GATE("ether0", 6, NULL, 0x210c, 9),
+       UNIPHIER_CLK_GATE("ether1", 7, NULL, 0x210c, 10),
        UNIPHIER_CLK_GATE("usb30", 12, NULL, 0x210c, 4),        /* =GIO0 */
        UNIPHIER_CLK_GATE("usb31-0", 13, NULL, 0x210c, 5),      /* =GIO1 */
        UNIPHIER_CLK_GATE("usb31-1", 14, NULL, 0x210c, 6),      /* =GIO1-1 */