drm/i915: rename BROADWATER and CRESTLINE to I965G and I965GM, respectively
authorJani Nikula <jani.nikula@intel.com>
Wed, 7 Dec 2016 10:13:04 +0000 (12:13 +0200)
committerJani Nikula <jani.nikula@intel.com>
Wed, 7 Dec 2016 13:18:33 +0000 (15:18 +0200)
Add more consistency to our naming. Pineview remains the outlier. Keep
using code names for gen5+.

v2: rebased

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1481105584-23033-1-git-send-email-jani.nikula@intel.com
drivers/gpu/drm/i915/i915_debugfs.c
drivers/gpu/drm/i915/i915_drv.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/i915_gem_internal.c
drivers/gpu/drm/i915/i915_pci.c
drivers/gpu/drm/i915/intel_device_info.c
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_pm.c

index 95f7a5ef0e368b308540ba47b8d9aa83111eb0a6..00a36bf879935479d22fc0ec638fe776cc3f74ff 100644 (file)
@@ -1734,7 +1734,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
 
        if (HAS_PCH_SPLIT(dev_priv))
                sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
-       else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) ||
+       else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
                 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
                sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
        else if (IS_I915GM(dev_priv))
index ae583c79c19f7cf98b2611ec30cd75a6353e8f33..1a7ac2eefe97def1efc361f6911b7145afdf3fec 100644 (file)
@@ -1033,7 +1033,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
         * behaviour if any general state is accessed within a page above 4GB,
         * which also needs to be handled carefully.
         */
-       if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv)) {
+       if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
                ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
 
                if (ret) {
index dc59670160e1aaeb0ec3d2f298e66a40a5decfd6..e5465b330886808e14251f24b6ddc6c8f9469192 100644 (file)
@@ -755,8 +755,8 @@ enum intel_platform {
        INTEL_I945GM,
        INTEL_G33,
        INTEL_PINEVIEW,
-       INTEL_BROADWATER,
-       INTEL_CRESTLINE,
+       INTEL_I965G,
+       INTEL_I965GM,
        INTEL_G4X,
        INTEL_IRONLAKE,
        INTEL_SANDYBRIDGE,
@@ -2522,8 +2522,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_I915GM(dev_priv)    (INTEL_DEVID(dev_priv) == 0x2592)
 #define IS_I945G(dev_priv)     (INTEL_DEVID(dev_priv) == 0x2772)
 #define IS_I945GM(dev_priv)    ((dev_priv)->info.platform == INTEL_I945GM)
-#define IS_BROADWATER(dev_priv)        ((dev_priv)->info.platform == INTEL_BROADWATER)
-#define IS_CRESTLINE(dev_priv) ((dev_priv)->info.platform == INTEL_CRESTLINE)
+#define IS_I965G(dev_priv)     ((dev_priv)->info.platform == INTEL_I965G)
+#define IS_I965GM(dev_priv)    ((dev_priv)->info.platform == INTEL_I965GM)
 #define IS_GM45(dev_priv)      (INTEL_DEVID(dev_priv) == 0x2A42)
 #define IS_G4X(dev_priv)       ((dev_priv)->info.platform == INTEL_G4X)
 #define IS_PINEVIEW_G(dev_priv)        (INTEL_DEVID(dev_priv) == 0xa001)
index ca0bb837a57f8557dc440a8cc67bd19c8e32b3ee..dd1a34ac830f7054e15aeb49d9d095ea4f1af2f3 100644 (file)
@@ -3999,7 +3999,7 @@ i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size)
                goto fail;
 
        mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
-       if (IS_CRESTLINE(dev_priv) || IS_BROADWATER(dev_priv)) {
+       if (IS_I965GM(dev_priv) || IS_I965G(dev_priv)) {
                /* 965gm cannot relocate objects above 4GiB. */
                mask &= ~__GFP_HIGHMEM;
                mask |= __GFP_DMA32;
index 08d26306d40eddf23665fca9989d53e6329079b5..2222863e505fd67b970e2a70005565ef01673498 100644 (file)
@@ -71,7 +71,7 @@ i915_gem_object_get_pages_internal(struct drm_i915_gem_object *obj)
 #endif
 
        gfp = GFP_KERNEL | __GFP_HIGHMEM | __GFP_RECLAIMABLE;
-       if (IS_CRESTLINE(i915) || IS_BROADWATER(i915)) {
+       if (IS_I965GM(i915) || IS_I965G(i915)) {
                /* 965gm cannot relocate objects above 4GiB. */
                gfp &= ~__GFP_HIGHMEM;
                gfp |= __GFP_DMA32;
index c0bcf323dbf0c85b7858e29e9e8d38c753aff1b0..99e8eed0a1fceaea0bfb59359d18734f6bffd207 100644 (file)
@@ -156,14 +156,14 @@ static const struct intel_device_info intel_pineview_info = {
 
 static const struct intel_device_info intel_i965g_info = {
        GEN4_FEATURES,
-       .platform = INTEL_BROADWATER,
+       .platform = INTEL_I965G,
        .has_overlay = 1,
        .hws_needs_physical = 1,
 };
 
 static const struct intel_device_info intel_i965gm_info = {
        GEN4_FEATURES,
-       .platform = INTEL_CRESTLINE,
+       .platform = INTEL_I965GM,
        .is_mobile = 1, .has_fbc = 1,
        .has_overlay = 1,
        .supports_tv = 1,
index 23b040743a6caaa67799941c5855f52c03908820..6f4cd4fca9577404e7d3edee76d321422645746b 100644 (file)
@@ -36,8 +36,8 @@ static const char * const platform_names[] = {
        PLATFORM_NAME(I945GM),
        PLATFORM_NAME(G33),
        PLATFORM_NAME(PINEVIEW),
-       PLATFORM_NAME(BROADWATER),
-       PLATFORM_NAME(CRESTLINE),
+       PLATFORM_NAME(I965G),
+       PLATFORM_NAME(I965GM),
        PLATFORM_NAME(G4X),
        PLATFORM_NAME(IRONLAKE),
        PLATFORM_NAME(SANDYBRIDGE),
index a88c810dbf6b51e3ba71ef0f34d0a9ab1e87076b..ab5ba7e084243b436e9064b8a5c8a0b6092c6282 100644 (file)
@@ -2150,7 +2150,7 @@ static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_pr
 {
        if (INTEL_INFO(dev_priv)->gen >= 9)
                return 256 * 1024;
-       else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
+       else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
                 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                return 128 * 1024;
        else if (INTEL_INFO(dev_priv)->gen >= 4)
@@ -7568,7 +7568,7 @@ static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
                vco_table = ctg_vco;
        else if (IS_G4X(dev_priv))
                vco_table = elk_vco;
-       else if (IS_CRESTLINE(dev_priv))
+       else if (IS_I965GM(dev_priv))
                vco_table = cl_vco;
        else if (IS_PINEVIEW(dev_priv))
                vco_table = pnv_vco;
@@ -16108,14 +16108,14 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
        else if (IS_GEN5(dev_priv))
                dev_priv->display.get_display_clock_speed =
                        ilk_get_display_clock_speed;
-       else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
+       else if (IS_I945G(dev_priv) || IS_I965G(dev_priv) ||
                 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
                dev_priv->display.get_display_clock_speed =
                        i945_get_display_clock_speed;
        else if (IS_GM45(dev_priv))
                dev_priv->display.get_display_clock_speed =
                        gm45_get_display_clock_speed;
-       else if (IS_CRESTLINE(dev_priv))
+       else if (IS_I965GM(dev_priv))
                dev_priv->display.get_display_clock_speed =
                        i965gm_get_display_clock_speed;
        else if (IS_PINEVIEW(dev_priv))
index d414c870ce6d07143c140a475c4e59ee70c3689e..c6fe59944a0bd47849f4accf2159a7726d6ebc62 100644 (file)
@@ -321,7 +321,7 @@ static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enabl
                was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
                I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
                POSTING_READ(FW_BLC_SELF_VLV);
-       } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
+       } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
                was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
                I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
                POSTING_READ(FW_BLC_SELF);
@@ -7643,9 +7643,9 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
                dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
        else if (IS_G4X(dev_priv))
                dev_priv->display.init_clock_gating = g4x_init_clock_gating;
-       else if (IS_CRESTLINE(dev_priv))
+       else if (IS_I965GM(dev_priv))
                dev_priv->display.init_clock_gating = crestline_init_clock_gating;
-       else if (IS_BROADWATER(dev_priv))
+       else if (IS_I965G(dev_priv))
                dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
        else if (IS_GEN3(dev_priv))
                dev_priv->display.init_clock_gating = gen3_init_clock_gating;