drm/radeon/kms: add cayman specific fence_ring_emit

cayman is wb only and doesn't have a VC.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index d0d23c547643995ac1d28e9bd35f4c3befdb618d..26d06644293405c80975d39f9ceb0d8e74e03d25 100644 (file)
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1009,6 +1009,27 @@ void cayman_pcie_gart_fini(struct radeon_device *rdev)
 /*
  * CP.
  */
+void cayman_fence_ring_emit(struct radeon_device *rdev,
+                           struct radeon_fence *fence)
+{
+       struct radeon_ring *ring = &rdev->ring[fence->ring];
+       u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
+
+       /* flush read cache over gart */
+       radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
+       radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
+       radeon_ring_write(ring, 0xFFFFFFFF);
+       radeon_ring_write(ring, 0);
+       radeon_ring_write(ring, 10); /* poll interval */
+       /* EVENT_WRITE_EOP - flush caches, send int */
+       radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
+       radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
+       radeon_ring_write(ring, addr & 0xffffffff);
+       radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
+       radeon_ring_write(ring, fence->seq);
+       radeon_ring_write(ring, 0);
+}
+
 static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
 {
        if (enable)

diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 4672869cdb265f0d4f0bd5b58ea99ee5afa761ec..e8d8124834b3939dc56b914a498c85beb2087905 100644 (file)
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -411,6 +411,10 @@
 #define        CP_ME_RAM_DATA                                  0xC160
 #define        CP_DEBUG                                        0xC1FC
 
+#define VGT_EVENT_INITIATOR                             0x28a90
+#       define CACHE_FLUSH_AND_INV_EVENT_TS                     (0x14 << 0)
+#       define CACHE_FLUSH_AND_INV_EVENT                        (0x16 << 0)
+
 /*
  * PM4
  */
@@ -494,7 +498,27 @@
 #define                PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
 #define        PACKET3_COND_WRITE                              0x45
 #define        PACKET3_EVENT_WRITE                             0x46
+#define                EVENT_TYPE(x)                           ((x) << 0)
+#define                EVENT_INDEX(x)                          ((x) << 8)
+                /* 0 - any non-TS event
+                * 1 - ZPASS_DONE
+                * 2 - SAMPLE_PIPELINESTAT
+                * 3 - SAMPLE_STREAMOUTSTAT*
+                * 4 - *S_PARTIAL_FLUSH
+                * 5 - TS events
+                */
 #define        PACKET3_EVENT_WRITE_EOP                         0x47
+#define                DATA_SEL(x)                             ((x) << 29)
+                /* 0 - discard
+                * 1 - send low 32bit data
+                * 2 - send 64bit data
+                * 3 - send 64bit counter value
+                */
+#define                INT_SEL(x)                              ((x) << 24)
+                /* 0 - none
+                * 1 - interrupt only (DATA_SEL = 0)
+                * 2 - interrupt when data write is confirmed
+                */
 #define        PACKET3_EVENT_WRITE_EOS                         0x48
 #define        PACKET3_PREAMBLE_CNTL                           0x4A
 #              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)

diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 558933c759cb83bccc7f58f24627b1afe7d68608..8493d406f5e3fbf07514bd6d4a7932a68ee539c4 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -966,17 +966,17 @@ static struct radeon_asic cayman_asic = {
        .ring = {
                [RADEON_RING_TYPE_GFX_INDEX] = {
                        .ib_execute = &evergreen_ring_ib_execute,
-                       .emit_fence = &r600_fence_ring_emit,
+                       .emit_fence = &cayman_fence_ring_emit,
                        .emit_semaphore = &r600_semaphore_ring_emit,
                },
                [CAYMAN_RING_TYPE_CP1_INDEX] = {
                        .ib_execute = &r600_ring_ib_execute,
-                       .emit_fence = &r600_fence_ring_emit,
+                       .emit_fence = &cayman_fence_ring_emit,
                        .emit_semaphore = &r600_semaphore_ring_emit,
                },
                [CAYMAN_RING_TYPE_CP2_INDEX] = {
                        .ib_execute = &r600_ring_ib_execute,
-                       .emit_fence = &r600_fence_ring_emit,
+                       .emit_fence = &cayman_fence_ring_emit,
                        .emit_semaphore = &r600_semaphore_ring_emit,
                }
        },

diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index a462fd9a2627d380a86a76c3edbe7a0d0c65b1a3..f0bab7878069a775d20f784175a54ad0f5ad20c8 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -429,6 +429,8 @@ int evergreen_blit_init(struct radeon_device *rdev);
 /*
  * cayman
  */
+void cayman_fence_ring_emit(struct radeon_device *rdev,
+                           struct radeon_fence *fence);
 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
 int cayman_init(struct radeon_device *rdev);
 void cayman_fini(struct radeon_device *rdev);