drm/i915/dp: limit DP link rate based on VBT on CNL+
authorJani Nikula <jani.nikula@intel.com>
Thu, 1 Feb 2018 11:03:43 +0000 (13:03 +0200)
committerJani Nikula <jani.nikula@intel.com>
Fri, 2 Feb 2018 07:50:51 +0000 (09:50 +0200)
We have the max DP link rate info available in VBT since BDB version
216, included in child device config since commit c4fb60b9aba9
("drm/i915/bios: add DP max link rate to VBT child device
struct"). Parse it and use it.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/a8b1364d1f2394fba3062b6ad11b474744ea4366.1517482774.git.jani.nikula@intel.com
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/intel_bios.c
drivers/gpu/drm/i915/intel_dp.c
drivers/gpu/drm/i915/intel_vbt_defs.h

index c67385ed0f663e15352e184cf3f78badd5273d1b..d1d8b1b8de460e2899bf0fb4121d26fe3dbb767e 100644 (file)
@@ -1282,6 +1282,7 @@ struct ddi_vbt_port_info {
 
        uint8_t dp_boost_level;
        uint8_t hdmi_boost_level;
+       int dp_max_link_rate;           /* 0 for not limited by VBT */
 };
 
 enum psr_lines_to_wait {
index cf3f8f1ba6f72601f5c0454203d021ec8757eb26..4e74aa2f16bc0d96d36dddbe76804335a3875d91 100644 (file)
@@ -1274,6 +1274,27 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
                DRM_DEBUG_KMS("VBT HDMI boost level for port %c: %d\n",
                              port_name(port), info->hdmi_boost_level);
        }
+
+       /* DP max link rate for CNL+ */
+       if (bdb_version >= 216) {
+               switch (child->dp_max_link_rate) {
+               default:
+               case VBT_DP_MAX_LINK_RATE_HBR3:
+                       info->dp_max_link_rate = 810000;
+                       break;
+               case VBT_DP_MAX_LINK_RATE_HBR2:
+                       info->dp_max_link_rate = 540000;
+                       break;
+               case VBT_DP_MAX_LINK_RATE_HBR:
+                       info->dp_max_link_rate = 270000;
+                       break;
+               case VBT_DP_MAX_LINK_RATE_LBR:
+                       info->dp_max_link_rate = 162000;
+                       break;
+               }
+               DRM_DEBUG_KMS("VBT DP max link rate for port %c: %d\n",
+                             port_name(port), info->dp_max_link_rate);
+       }
 }
 
 static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version)
index bee51051482677bf8b6c356f7f2daf1bac311df4..8503d182921b4c4d29a097990436a767bc7ff3ba 100644 (file)
@@ -268,8 +268,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
 {
        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
        struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+       const struct ddi_vbt_port_info *info =
+               &dev_priv->vbt.ddi_port_info[dig_port->base.port];
        const int *source_rates;
-       int size, max_rate = 0;
+       int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 
        /* This should only be done once */
        WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
@@ -293,6 +295,11 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
                size = ARRAY_SIZE(default_rates) - 1;
        }
 
+       if (max_rate && vbt_max_rate)
+               max_rate = min(max_rate, vbt_max_rate);
+       else if (vbt_max_rate)
+               max_rate = vbt_max_rate;
+
        if (max_rate)
                size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 
index 3d3feee9b5dd112675acd4f1b6bdf3c63a436e5b..458468237b5f94d4572e421194459c7ea150fb66 100644 (file)
@@ -320,6 +320,11 @@ enum vbt_gmbus_ddi {
        DDC_BUS_DDI_F,
 };
 
+#define VBT_DP_MAX_LINK_RATE_HBR3      0
+#define VBT_DP_MAX_LINK_RATE_HBR2      1
+#define VBT_DP_MAX_LINK_RATE_HBR       2
+#define VBT_DP_MAX_LINK_RATE_LBR       3
+
 /*
  * The child device config, aka the display device data structure, provides a
  * description of a port and its configuration on the platform.