PCI/CXL: Move CXL Vendor ID to pci_ids.h
authorDave Jiang <dave.jiang@intel.com>
Thu, 2 May 2024 16:57:30 +0000 (09:57 -0700)
committerBjorn Helgaas <bhelgaas@google.com>
Wed, 8 May 2024 18:18:33 +0000 (13:18 -0500)
Move PCI_DVSEC_VENDOR_ID_CXL in CXL private code to PCI_VENDOR_ID_CXL in
pci_ids.h in order to be utilized in PCI subsystem.

While the CXL Vendor ID (0x1e98) is not listed in the PCI SIG "Member
Companies" database at https://pcisig.com/membership/member-companies, the
SIG has confirmed that it is reserved by CXL.

Link: https://lore.kernel.org/r/20240502165851.1948523-2-dave.jiang@intel.com
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Link: https://lore.kernel.org/linux-cxl/20240402172323.GA1818777@bhelgaas/
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
[bhelgaas: update commit log]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
drivers/cxl/core/pci.c
drivers/cxl/core/regs.c
drivers/cxl/cxlpci.h
drivers/cxl/pci.c
drivers/perf/cxl_pmu.c
include/linux/pci_ids.h

index 0df09bd79408842441d4f865c9be052b7564a3c9..c496a9710d62ea4587c7e7b1e5a1d2c019331d40 100644 (file)
@@ -525,7 +525,7 @@ static int cxl_cdat_get_length(struct device *dev,
        __le32 response[2];
        int rc;
 
-       rc = pci_doe(doe_mb, PCI_DVSEC_VENDOR_ID_CXL,
+       rc = pci_doe(doe_mb, PCI_VENDOR_ID_CXL,
                     CXL_DOE_PROTOCOL_TABLE_ACCESS,
                     &request, sizeof(request),
                     &response, sizeof(response));
@@ -555,7 +555,7 @@ static int cxl_cdat_read_table(struct device *dev,
                __le32 request = CDAT_DOE_REQ(entry_handle);
                int rc;
 
-               rc = pci_doe(doe_mb, PCI_DVSEC_VENDOR_ID_CXL,
+               rc = pci_doe(doe_mb, PCI_VENDOR_ID_CXL,
                             CXL_DOE_PROTOCOL_TABLE_ACCESS,
                             &request, sizeof(request),
                             rsp, sizeof(*rsp) + remaining);
@@ -640,7 +640,7 @@ void read_cdat_data(struct cxl_port *port)
        if (!pdev)
                return;
 
-       doe_mb = pci_find_doe_mailbox(pdev, PCI_DVSEC_VENDOR_ID_CXL,
+       doe_mb = pci_find_doe_mailbox(pdev, PCI_VENDOR_ID_CXL,
                                      CXL_DOE_PROTOCOL_TABLE_ACCESS);
        if (!doe_mb) {
                dev_dbg(dev, "No CDAT mailbox\n");
index 372786f809555f66509186c3e3476af2fad0d7f8..da52fc9e234b009823f94e5caa8821a88a9ef05a 100644 (file)
@@ -313,7 +313,7 @@ int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type,
                .resource = CXL_RESOURCE_NONE,
        };
 
-       regloc = pci_find_dvsec_capability(pdev, PCI_DVSEC_VENDOR_ID_CXL,
+       regloc = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,
                                           CXL_DVSEC_REG_LOCATOR);
        if (!regloc)
                return -ENXIO;
index 93992a1c8eecf683edb72a5035e4a25872e64668..4da07727ab9cd15beb0f1f917d42a91bca171fb9 100644 (file)
@@ -13,7 +13,6 @@
  * "DVSEC" redundancies removed. When obvious, abbreviations may be used.
  */
 #define PCI_DVSEC_HEADER1_LENGTH_MASK  GENMASK(31, 20)
-#define PCI_DVSEC_VENDOR_ID_CXL                0x1E98
 
 /* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */
 #define CXL_DVSEC_PCIE_DEVICE                                  0
index 2ff361e756d66147d8d20969c376730ae2bcc90e..11047857329609d61aedd89a1f56bba7629f15bb 100644 (file)
@@ -817,7 +817,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
        cxlds->rcd = is_cxl_restricted(pdev);
        cxlds->serial = pci_get_dsn(pdev);
        cxlds->cxl_dvsec = pci_find_dvsec_capability(
-               pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE);
+               pdev, PCI_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE);
        if (!cxlds->cxl_dvsec)
                dev_warn(&pdev->dev,
                         "Device DVSEC not present, skip CXL.mem init\n");
index 308c9969642e1f149cdebd9f8aed7812adbc5f1f..a1b742b1a7350e9eab6f6606a9591c1dd96ca7f3 100644 (file)
@@ -345,7 +345,7 @@ static ssize_t cxl_pmu_event_sysfs_show(struct device *dev,
 
 /* For CXL spec defined events */
 #define CXL_PMU_EVENT_CXL_ATTR(_name, _gid, _msk)                      \
-       CXL_PMU_EVENT_ATTR(_name, PCI_DVSEC_VENDOR_ID_CXL, _gid, _msk)
+       CXL_PMU_EVENT_ATTR(_name, PCI_VENDOR_ID_CXL, _gid, _msk)
 
 static struct attribute *cxl_pmu_event_attrs[] = {
        CXL_PMU_EVENT_CXL_ATTR(clock_ticks,                     CXL_PMU_GID_CLOCK_TICKS, BIT(0)),
index a0c75e467df36f168f3aa920e6edcc2e1f70ef84..7dfbf6d96b3d88e0b6a358c920ce77b4d158a5dc 100644 (file)
 
 #define PCI_VENDOR_ID_ALIBABA          0x1ded
 
+#define PCI_VENDOR_ID_CXL              0x1e98
+
 #define PCI_VENDOR_ID_TEHUTI           0x1fc9
 #define PCI_DEVICE_ID_TEHUTI_3009      0x3009
 #define PCI_DEVICE_ID_TEHUTI_3010      0x3010