Merge tag 'amd-drm-fixes-5.10-2020-10-14' of git://people.freedesktop.org/~agd5f...
authorDave Airlie <airlied@redhat.com>
Sun, 18 Oct 2020 23:11:32 +0000 (09:11 +1000)
committerDave Airlie <airlied@redhat.com>
Sun, 18 Oct 2020 23:11:33 +0000 (09:11 +1000)
amd-drm-fixes-5.10-2020-10-14:

amdgpu:
- eDP fix
- BACO fix
- Kernel documentation fixes
- SMU7 mclk fix
- VCN1 hw bug workaround

amdkfd:
- kvfree vs kfree fix

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201014195403.4558-1-alexander.deucher@amd.com
Documentation/gpu/amdgpu.rst
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.h
drivers/gpu/drm/amd/amdkfd/kfd_crat.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
drivers/gpu/drm/amd/display/dc/core/dc.c
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

index 57047dcb8d19fb8279f6685818cfa015ae7f8019..1f9ea8221f80c5307d6dfc7cb88cc0b6d30494b0 100644 (file)
@@ -206,8 +206,8 @@ pp_power_profile_mode
 .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
    :doc: pp_power_profile_mode
 
-*_busy_percent
-~~~~~~~~~~~~~~
+\*_busy_percent
+~~~~~~~~~~~~~~~
 
 .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
    :doc: gpu_busy_percent
index 495c3d7bb2b2b468ced0c3ee06c27e69662e8c99..f3b7287e84c43ea433a8bbcc9a959842059517dd 100644 (file)
@@ -68,6 +68,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
 
        INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
        mutex_init(&adev->vcn.vcn_pg_lock);
+       mutex_init(&adev->vcn.vcn1_jpeg1_workaround);
        atomic_set(&adev->vcn.total_submission_cnt, 0);
        for (i = 0; i < adev->vcn.num_vcn_inst; i++)
                atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
@@ -237,6 +238,7 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
        }
 
        release_firmware(adev->vcn.fw);
+       mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
        mutex_destroy(&adev->vcn.vcn_pg_lock);
 
        return 0;
index 7a9b804bc988a49eda72beb4c32b27f15dd504f0..17691158f783e3f3604014512668312a5a8f77bd 100644 (file)
@@ -220,6 +220,7 @@ struct amdgpu_vcn {
        struct amdgpu_vcn_inst   inst[AMDGPU_MAX_VCN_INSTANCES];
        struct amdgpu_vcn_reg    internal;
        struct mutex             vcn_pg_lock;
+       struct mutex            vcn1_jpeg1_workaround;
        atomic_t                 total_submission_cnt;
 
        unsigned        harvest_config;
index bc300283b6abcf6cd5444127795d9943db4d411f..c600b61b5f45de1a974b71276515370ab7fec644 100644 (file)
@@ -33,6 +33,7 @@
 
 static void jpeg_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
 static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev);
+static void jpeg_v1_0_ring_begin_use(struct amdgpu_ring *ring);
 
 static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)
 {
@@ -564,8 +565,8 @@ static const struct amdgpu_ring_funcs jpeg_v1_0_decode_ring_vm_funcs = {
        .insert_start = jpeg_v1_0_decode_ring_insert_start,
        .insert_end = jpeg_v1_0_decode_ring_insert_end,
        .pad_ib = amdgpu_ring_generic_pad_ib,
-       .begin_use = vcn_v1_0_ring_begin_use,
-       .end_use = amdgpu_vcn_ring_end_use,
+       .begin_use = jpeg_v1_0_ring_begin_use,
+       .end_use = vcn_v1_0_ring_end_use,
        .emit_wreg = jpeg_v1_0_decode_ring_emit_wreg,
        .emit_reg_wait = jpeg_v1_0_decode_ring_emit_reg_wait,
        .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
@@ -586,3 +587,22 @@ static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev)
 {
        adev->jpeg.inst->irq.funcs = &jpeg_v1_0_irq_funcs;
 }
+
+static void jpeg_v1_0_ring_begin_use(struct amdgpu_ring *ring)
+{
+       struct  amdgpu_device *adev = ring->adev;
+       bool    set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
+       int             cnt = 0;
+
+       mutex_lock(&adev->vcn.vcn1_jpeg1_workaround);
+
+       if (amdgpu_fence_wait_empty(&adev->vcn.inst->ring_dec))
+               DRM_ERROR("JPEG dec: vcn dec ring may not be empty\n");
+
+       for (cnt = 0; cnt < adev->vcn.num_enc_rings; cnt++) {
+               if (amdgpu_fence_wait_empty(&adev->vcn.inst->ring_enc[cnt]))
+                       DRM_ERROR("JPEG dec: vcn enc ring[%d] may not be empty\n", cnt);
+       }
+
+       vcn_v1_0_set_pg_for_begin_use(ring, set_clocks);
+}
index 73699eafb51eda99c3ec12efda0d1e6b5b7e91d7..86e1ef732ebecebc6e1789644d97e12986e113a5 100644 (file)
@@ -54,6 +54,7 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
                                int inst_idx, struct dpg_pause_state *new_state);
 
 static void vcn_v1_0_idle_work_handler(struct work_struct *work);
+static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring);
 
 /**
  * vcn_v1_0_early_init - set function pointers
@@ -1804,11 +1805,24 @@ static void vcn_v1_0_idle_work_handler(struct work_struct *work)
        }
 }
 
-void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring)
+static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring)
 {
-       struct amdgpu_device *adev = ring->adev;
+       struct  amdgpu_device *adev = ring->adev;
        bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
 
+       mutex_lock(&adev->vcn.vcn1_jpeg1_workaround);
+
+       if (amdgpu_fence_wait_empty(&ring->adev->jpeg.inst->ring_dec))
+               DRM_ERROR("VCN dec: jpeg dec ring may not be empty\n");
+
+       vcn_v1_0_set_pg_for_begin_use(ring, set_clocks);
+
+}
+
+void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks)
+{
+       struct amdgpu_device *adev = ring->adev;
+
        if (set_clocks) {
                amdgpu_gfx_off_ctrl(adev, false);
                if (adev->pm.dpm_enabled)
@@ -1844,6 +1858,12 @@ void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring)
        }
 }
 
+void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring)
+{
+       schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
+       mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround);
+}
+
 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
        .name = "vcn_v1_0",
        .early_init = vcn_v1_0_early_init,
@@ -1891,7 +1911,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
        .insert_end = vcn_v1_0_dec_ring_insert_end,
        .pad_ib = amdgpu_ring_generic_pad_ib,
        .begin_use = vcn_v1_0_ring_begin_use,
-       .end_use = amdgpu_vcn_ring_end_use,
+       .end_use = vcn_v1_0_ring_end_use,
        .emit_wreg = vcn_v1_0_dec_ring_emit_wreg,
        .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait,
        .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
@@ -1923,7 +1943,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
        .insert_end = vcn_v1_0_enc_ring_insert_end,
        .pad_ib = amdgpu_ring_generic_pad_ib,
        .begin_use = vcn_v1_0_ring_begin_use,
-       .end_use = amdgpu_vcn_ring_end_use,
+       .end_use = vcn_v1_0_ring_end_use,
        .emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
        .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait,
        .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
index f67d7391fc21c9759181ea2bd16149c2bdd8b41d..1f1cc7f0ece7050c37fc6eb62453a82db37f694b 100644 (file)
@@ -24,7 +24,8 @@
 #ifndef __VCN_V1_0_H__
 #define __VCN_V1_0_H__
 
-void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring);
+void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring);
+void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks);
 
 extern const struct amdgpu_ip_block_version vcn_v1_0_ip_block;
 
index d2981524dba0b231166da18037acb48eb564bb32..5e2254b9e93165bb03af515256ebf1e3a67aead6 100644 (file)
@@ -1426,5 +1426,5 @@ int kfd_create_crat_image_virtual(void **crat_image, size_t *size,
  */
 void kfd_destroy_crat_image(void *crat_image)
 {
-       kfree(crat_image);
+       kvfree(crat_image);
 }
index 9c1e003d9c29553579bf008eebf465fc69c50c7a..34f6369bf51fb34d8fb27860928887a86568b21e 100644 (file)
@@ -149,6 +149,8 @@ struct amdgpu_dm_backlight_caps {
  * @cached_state: Caches device atomic state for suspend/resume
  * @cached_dc_state: Cached state of content streams
  * @compressor: Frame buffer compression buffer. See &struct dm_comressor_info
+ * @force_timing_sync: set via debugfs. When set, indicates that all connected
+ *                    displays will be forced to synchronize.
  */
 struct amdgpu_display_manager {
 
index 2a725a5fba40239ca4e42214f9a0afd7028f5c42..1eb29c3621224a3d4bfa1fa5a9e3dc0f13bba74b 100644 (file)
@@ -848,7 +848,7 @@ static void disable_vbios_mode_if_required(
                struct dc *dc,
                struct dc_state *context)
 {
-       unsigned int i;
+       unsigned int i, j;
 
        /* check if timing_changed, disable stream*/
        for (i = 0; i < dc->res_pool->pipe_count; i++) {
@@ -872,10 +872,10 @@ static void disable_vbios_mode_if_required(
 
                        enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
                        if (enc_inst != ENGINE_ID_UNKNOWN) {
-                               for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
-                                       if (dc->res_pool->stream_enc[i]->id == enc_inst) {
-                                               tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
-                                                       dc->res_pool->stream_enc[i]);
+                               for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
+                                       if (dc->res_pool->stream_enc[j]->id == enc_inst) {
+                                               tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg(
+                                                       dc->res_pool->stream_enc[j]);
                                                break;
                                        }
                                }
index 3bf8be4d107beba7a8ddb9ebcad231452e30283b..1e8919b0acdb262c714f4229be9855c64bbf436c 100644 (file)
@@ -2883,7 +2883,7 @@ static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr,
                if (hwmgr->is_kicker)
                        switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
                else
-                       switch_limit_us = data->is_memory_gddr5 ? 190 : 150;
+                       switch_limit_us = data->is_memory_gddr5 ? 200 : 150;
                break;
        case CHIP_VEGAM:
                switch_limit_us = 30;
index e41fd6ea64518fc7db8cc27ab244469d201bced0..b1e5ec01527b82d7035ba705fe5b1ad4de4188c0 100644 (file)
@@ -417,6 +417,9 @@ static int smu_early_init(void *handle)
        smu->pm_enabled = !!amdgpu_dpm;
        smu->is_apu = false;
        mutex_init(&smu->mutex);
+       mutex_init(&smu->smu_baco.mutex);
+       smu->smu_baco.state = SMU_BACO_STATE_EXIT;
+       smu->smu_baco.platform_support = false;
 
        return smu_set_funcs(adev);
 }
@@ -795,10 +798,6 @@ static int smu_sw_init(void *handle)
        bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
        bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
 
-       mutex_init(&smu->smu_baco.mutex);
-       smu->smu_baco.state = SMU_BACO_STATE_EXIT;
-       smu->smu_baco.platform_support = false;
-
        mutex_init(&smu->sensor_lock);
        mutex_init(&smu->metrics_lock);
        mutex_init(&smu->message_lock);