clk: mmp2: Move thermal register defines up a bit

A trivial change to keep the sorting sane. The APBC registers are happier
when they are grouped together, instead of mixed with the APMU ones.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200519224151.2074597-6-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
index 52dc8b43acd9ad5213297f4b1ee8eed286038f62..524574187c17a8761bb285e4ef4f76c8ce899446 100644 (file)
--- a/drivers/clk/mmp/clk-of-mmp2.c
+++ b/drivers/clk/mmp/clk-of-mmp2.c
@@ -45,6 +45,10 @@
 #define APBC_SSP1      0x54
 #define APBC_SSP2      0x58
 #define APBC_SSP3      0x5c
+#define APBC_THERMAL0  0x90
+#define APBC_THERMAL1  0x98
+#define APBC_THERMAL2  0x9c
+#define APBC_THERMAL3  0xa0
 #define APMU_SDH0      0x54
 #define APMU_SDH1      0x58
 #define APMU_SDH2      0xe8
@@ -55,10 +59,6 @@
 #define APMU_DISP1     0x110
 #define APMU_CCIC0     0x50
 #define APMU_CCIC1     0xf4
-#define APBC_THERMAL0  0x90
-#define APBC_THERMAL1  0x98
-#define APBC_THERMAL2  0x9c
-#define APBC_THERMAL3  0xa0
 #define APMU_USBHSIC0  0xf8
 #define APMU_USBHSIC1  0xfc
 #define APMU_GPU       0xcc