drm/sun4i: drc: Make sure we enforce the clock rate
authorMaxime Ripard <maxime@cerno.tech>
Tue, 7 Jan 2020 16:59:57 +0000 (17:59 +0100)
committerMaxime Ripard <maxime@cerno.tech>
Wed, 8 Jan 2020 08:14:08 +0000 (09:14 +0100)
The DRC needs to run at 300MHz to be functional. This was done so far
using assigned-clocks in the device tree, but that is easy to forget, and
doesn't provide any other guarantee than the rate is going to be roughly
the one requested at probe time.

Therefore it's pretty fragile, so let's just use the exclusive clock API to
enforce it.

Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20200107165957.672435-2-maxime@cerno.tech
drivers/gpu/drm/sun4i/sun6i_drc.c

index f7ab72244796c52742d9ba2f99c4a884f7f7e8cf..4fbe9a6b5182c48c9c0f0870706ca801df5d34c1 100644 (file)
@@ -56,6 +56,13 @@ static int sun6i_drc_bind(struct device *dev, struct device *master,
                ret = PTR_ERR(drc->mod_clk);
                goto err_disable_bus_clk;
        }
+
+       ret = clk_set_rate_exclusive(drc->mod_clk, 300000000);
+       if (ret) {
+               dev_err(dev, "Couldn't set the module clock frequency\n");
+               goto err_disable_bus_clk;
+       }
+
        clk_prepare_enable(drc->mod_clk);
 
        return 0;
@@ -72,6 +79,7 @@ static void sun6i_drc_unbind(struct device *dev, struct device *master,
 {
        struct sun6i_drc *drc = dev_get_drvdata(dev);
 
+       clk_rate_exclusive_put(drc->mod_clk);
        clk_disable_unprepare(drc->mod_clk);
        clk_disable_unprepare(drc->bus_clk);
        reset_control_assert(drc->reset);