drm/amd/pp: Add OD driver clock/voltage display on smu7

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 68f2c8484187200bd25cb2a16f7a1acaac8475ed..103837c7a48cc0b05b2cbb27f41e650d04fc497f 100644 (file)
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -107,6 +107,8 @@ enum pp_clock_type {
        PP_SCLK,
        PP_MCLK,
        PP_PCIE,
+       OD_SCLK,
+       OD_MCLK,
 };
 
 enum amd_pp_sensors {

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 80bf6693d1e7c6ce92a69361ef312c951a5cd7f0..4ccc9101f2e355c9c48c3e9ed2b5bdbc2cb14cb0 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4355,6 +4355,9 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
        struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
        struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
        struct smu7_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
+       struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
+       struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
+       struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
        int i, now, size = 0;
        uint32_t clock, pcie_speed;
 
@@ -4407,6 +4410,24 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
                                        (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "",
                                        (i == now) ? "*" : "");
                break;
+       case OD_SCLK:
+               if (hwmgr->od_enabled) {
+                       size = sprintf(buf, "%s: \n", "OD_SCLK");
+                       for (i = 0; i < odn_sclk_table->num_of_pl; i++)
+                               size += sprintf(buf + size, "%d: %10uMhz %10u mV\n",
+                                       i, odn_sclk_table->entries[i].clock / 100,
+                                       odn_sclk_table->entries[i].vddc);
+               }
+               break;
+       case OD_MCLK:
+               if (hwmgr->od_enabled) {
+                       size = sprintf(buf, "%s: \n", "OD_MCLK");
+                       for (i = 0; i < odn_mclk_table->num_of_pl; i++)
+                               size += sprintf(buf + size, "%d: %10uMhz %10u mV\n",
+                                       i, odn_mclk_table->entries[i].clock / 100,
+                                       odn_mclk_table->entries[i].vddc);
+               }
+               break;
        default:
                break;
        }