riscv: dts: microchip: add the mpfs' fabric clock control

The "fabric clocks" in current PolarFire SoC device trees are not
really fixed clocks. Their frequency is set by the bitstream, so having
them located in -fabric.dtsi is not a problem - they're just as "fixed"
as the IP blocks etc used in the FPGA fabric.
However, their configuration can be read at runtime (and to an extent
they can be controlled, although the intended usage is static
configurations set by the bitstream) through the system controller bus.

In the v2022.09 icicle kit reference design a single CCC (north-west
corner) is enabled, using a 50 MHz off-chip oscillator as its reference.

Updating to the v2022.09 icicle kit reference design is required, as
prior to this release, the CCC was not fixed & could change for any
given run of the synthesis tool.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index 24b1cfb9a73e432f2881595ecf2a4319aa6d6fd9..9d1514a48f9cfb1b1bcdec50fa0b9de89c7fee8c 100644 (file)
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -10,7 +10,7 @@
                reg = <0x0 0x40000000 0x0 0xF0>;
                microchip,sync-update-mask = /bits/ 32 <0>;
                #pwm-cells = <2>;
-               clocks = <&fabric_clk3>;
+               clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>;
                status = "disabled";
        };
 
@@ -19,25 +19,13 @@
                reg = <0x0 0x40000200 0x0 0x100>;
                #address-cells = <1>;
                #size-cells = <0>;
-               clocks = <&fabric_clk3>;
+               clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>;
                interrupt-parent = <&plic>;
                interrupts = <122>;
                clock-frequency = <100000>;
                status = "disabled";
        };
 
-       fabric_clk3: fabric-clk3 {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <50000000>;
-       };
-
-       fabric_clk1: fabric-clk1 {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <125000000>;
-       };
-
        pcie: pcie@3000000000 {
                compatible = "microchip,pcie-host-1.0";
                #address-cells = <0x3>;
@@ -54,7 +42,7 @@
                                <0 0 0 3 &pcie_intc 2>,
                                <0 0 0 4 &pcie_intc 3>;
                interrupt-map-mask = <0 0 0 7>;
-               clocks = <&fabric_clk1>, <&fabric_clk3>;
+               clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>;
                clock-names = "fic1", "fic3";
                ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>;
                dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
@@ -67,4 +55,17 @@
                        interrupt-controller;
                };
        };
+
+       refclk_ccc: cccrefclk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+       };
+};
+
+&ccc_nw {
+       clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
+                <&refclk_ccc>, <&refclk_ccc>;
+       clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
+                     "dll0_ref", "dll1_ref";
+       status = "okay";
 };

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index ec7b7c2a3ce2827e819f31b855f7ced83d55e482..c3cb53f7059c870f7228d5e2d293ce273be284e9 100644 (file)
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -149,6 +149,10 @@
        clock-frequency = <125000000>;
 };
 
+&refclk_ccc {
+       clock-frequency = <50000000>;
+};
+
 &rtc {
        status = "okay";
 };

diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 8f463399a5687ef81250dd4d320f0456f18f85b2..0a9bb84af4386936ba913f34bb6bd40ffead98fc 100644 (file)
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -236,6 +236,38 @@
                        #clock-cells = <1>;
                };
 
+               ccc_se: clock-controller@38010000 {
+                       compatible = "microchip,mpfs-ccc";
+                       reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>,
+                             <0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>;
+                       #clock-cells = <1>;
+                       status = "disabled";
+               };
+
+               ccc_ne: clock-controller@38040000 {
+                       compatible = "microchip,mpfs-ccc";
+                       reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>,
+                             <0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>;
+                       #clock-cells = <1>;
+                       status = "disabled";
+               };
+
+               ccc_nw: clock-controller@38100000 {
+                       compatible = "microchip,mpfs-ccc";
+                       reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>,
+                             <0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>;
+                       #clock-cells = <1>;
+                       status = "disabled";
+               };
+
+               ccc_sw: clock-controller@38400000 {
+                       compatible = "microchip,mpfs-ccc";
+                       reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>,
+                             <0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>;
+                       #clock-cells = <1>;
+                       status = "disabled";
+               };
+
                mmuart0: serial@20000000 {
                        compatible = "ns16550a";
                        reg = <0x0 0x20000000 0x0 0x400>;