drm/i915: split clock gating init from display vtable

This function is only used inside intel_pm.c

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/95d626a7329ab5779804762894e304e12c6dbe1f.1632869550.git.jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 97bfeadaab94e826999e90e5fea5f538537e134b..bbb28b854f46e84ec0ee46bdac214b435bb3bcec 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -323,6 +323,11 @@ struct intel_crtc;
 struct intel_limit;
 struct dpll;
 
+/* functions used internal in intel_pm.c */
+struct drm_i915_clock_gating_funcs {
+       void (*init_clock_gating)(struct drm_i915_private *dev_priv);
+};
+
 struct drm_i915_display_funcs {
        void (*get_cdclk)(struct drm_i915_private *dev_priv,
                          struct intel_cdclk_config *cdclk_config);
@@ -365,7 +370,6 @@ struct drm_i915_display_funcs {
                                    const struct drm_connector_state *old_conn_state);
        void (*fdi_link_train)(struct intel_crtc *crtc,
                               const struct intel_crtc_state *crtc_state);
-       void (*init_clock_gating)(struct drm_i915_private *dev_priv);
        void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
        /* clock updates for mode set */
        /* cursor updates */
@@ -954,6 +958,9 @@ struct drm_i915_private {
        /* unbound hipri wq for page flips/plane updates */
        struct workqueue_struct *flip_wq;
 
+       /* pm private clock gating functions */
+       struct drm_i915_clock_gating_funcs clock_gating_funcs;
+
        /* Display functions */
        struct drm_i915_display_funcs display;
 

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 11c9df62391dfda969ec13e949c77185b98d7086..34d6faee89698374a765ae1801518d9edb69edcd 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7869,7 +7869,7 @@ static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
 
 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       dev_priv->display.init_clock_gating(dev_priv);
+       dev_priv->clock_gating_funcs.init_clock_gating(dev_priv);
 }
 
 void intel_suspend_hw(struct drm_i915_private *dev_priv)
@@ -7896,52 +7896,52 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
        if (IS_ALDERLAKE_P(dev_priv))
-               dev_priv->display.init_clock_gating = adlp_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = adlp_init_clock_gating;
        else if (IS_DG1(dev_priv))
-               dev_priv->display.init_clock_gating = dg1_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = dg1_init_clock_gating;
        else if (GRAPHICS_VER(dev_priv) == 12)
-               dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = gen12lp_init_clock_gating;
        else if (GRAPHICS_VER(dev_priv) == 11)
-               dev_priv->display.init_clock_gating = icl_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = icl_init_clock_gating;
        else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
-               dev_priv->display.init_clock_gating = cfl_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = cfl_init_clock_gating;
        else if (IS_SKYLAKE(dev_priv))
-               dev_priv->display.init_clock_gating = skl_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = skl_init_clock_gating;
        else if (IS_KABYLAKE(dev_priv))
-               dev_priv->display.init_clock_gating = kbl_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = kbl_init_clock_gating;
        else if (IS_BROXTON(dev_priv))
-               dev_priv->display.init_clock_gating = bxt_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = bxt_init_clock_gating;
        else if (IS_GEMINILAKE(dev_priv))
-               dev_priv->display.init_clock_gating = glk_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = glk_init_clock_gating;
        else if (IS_BROADWELL(dev_priv))
-               dev_priv->display.init_clock_gating = bdw_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = bdw_init_clock_gating;
        else if (IS_CHERRYVIEW(dev_priv))
-               dev_priv->display.init_clock_gating = chv_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = chv_init_clock_gating;
        else if (IS_HASWELL(dev_priv))
-               dev_priv->display.init_clock_gating = hsw_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = hsw_init_clock_gating;
        else if (IS_IVYBRIDGE(dev_priv))
-               dev_priv->display.init_clock_gating = ivb_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = ivb_init_clock_gating;
        else if (IS_VALLEYVIEW(dev_priv))
-               dev_priv->display.init_clock_gating = vlv_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = vlv_init_clock_gating;
        else if (GRAPHICS_VER(dev_priv) == 6)
-               dev_priv->display.init_clock_gating = gen6_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = gen6_init_clock_gating;
        else if (GRAPHICS_VER(dev_priv) == 5)
-               dev_priv->display.init_clock_gating = ilk_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = ilk_init_clock_gating;
        else if (IS_G4X(dev_priv))
-               dev_priv->display.init_clock_gating = g4x_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = g4x_init_clock_gating;
        else if (IS_I965GM(dev_priv))
-               dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = i965gm_init_clock_gating;
        else if (IS_I965G(dev_priv))
-               dev_priv->display.init_clock_gating = i965g_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = i965g_init_clock_gating;
        else if (GRAPHICS_VER(dev_priv) == 3)
-               dev_priv->display.init_clock_gating = gen3_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = gen3_init_clock_gating;
        else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
-               dev_priv->display.init_clock_gating = i85x_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = i85x_init_clock_gating;
        else if (GRAPHICS_VER(dev_priv) == 2)
-               dev_priv->display.init_clock_gating = i830_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = i830_init_clock_gating;
        else {
                MISSING_CASE(INTEL_DEVID(dev_priv));
-               dev_priv->display.init_clock_gating = nop_init_clock_gating;
+               dev_priv->clock_gating_funcs.init_clock_gating = nop_init_clock_gating;
        }
 }