drm/i915/dg2: Return Wa_22012654132 to just specific steppings

Programming of the ENABLE_PREFETCH_INTO_IC bit originally showed up in
both the general DG2 tuning guide (applicable to all DG2
variants/steppings) and under Wa_22012654132 (applicable only to
specific steppings).  It has now been removed from the tuning guide, and
the guidance is to only program it in the specific steppings associated
with the workaround.

Bspec: 68331
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221213234119.2963317-1-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 38746a71fc1f16c1827f97fa0b9078f3d4648b30..c1c2ea303e9dde3553f96cd531fb73b710d056ef 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2912,20 +2912,6 @@ add_render_compute_tuning_settings(struct drm_i915_private *i915,
        if (IS_DG2(i915)) {
                wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
                wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
-
-               /*
-                * This is also listed as Wa_22012654132 for certain DG2
-                * steppings, but the tuning setting programming is a superset
-                * since it applies to all DG2 variants and steppings.
-                *
-                * Note that register 0xE420 is write-only and cannot be read
-                * back for verification on DG2 (due to Wa_14012342262), so
-                * we need to explicitly skip the readback.
-                */
-               wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
-                          _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
-                          0 /* write-only, so skip validation */,
-                          true);
        }
 
        /*
@@ -3021,6 +3007,19 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
                /* Wa_18017747507:dg2 */
                wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
        }
+
+       if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_C0) || IS_DG2_G11(i915))
+               /*
+                * Wa_22012654132
+                *
+                * Note that register 0xE420 is write-only and cannot be read
+                * back for verification on DG2 (due to Wa_14012342262), so
+                * we need to explicitly skip the readback.
+                */
+               wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
+                          _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
+                          0 /* write-only, so skip validation */,
+                          true);
 }
 
 static void