Merge branch 'spi-5.3' into spi-linus
authorMark Brown <broonie@kernel.org>
Sun, 15 Sep 2019 09:32:04 +0000 (10:32 +0100)
committerMark Brown <broonie@kernel.org>
Sun, 15 Sep 2019 09:32:04 +0000 (10:32 +0100)
Documentation/devicetree/bindings/spi/spi-controller.yaml
drivers/spi/spi-bcm-qspi.c
drivers/spi/spi-bcm2835.c
drivers/spi/spi-dw-pci.c
drivers/spi/spi-fsl-dspi.c
drivers/spi/spi-uniphier.c
drivers/spi/spi-zynq-qspi.c

index a02e2fe2bfb22350773759da4b27fc13800f1c49..732339275848c12a52c438656f97e3e74a44b9ff 100644 (file)
@@ -31,7 +31,7 @@ properties:
       If that property is used, the number of chip selects will be
       increased automatically with max(cs-gpios, hardware chip selects).
 
-      So if, for example, the controller has 2 CS lines, and the
+      So if, for example, the controller has 4 CS lines, and the
       cs-gpios looks like this
         cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>;
 
index 902bdbfedea8752099c1772b4026b61fb4fa0464..0dbfd2496ab8f5a2a62a97baf467537e417a0133 100644 (file)
@@ -343,7 +343,7 @@ static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi,
 {
        int bpc = 0, bpp = 0;
        u8 command = op->cmd.opcode;
-       int width  = op->cmd.buswidth ? op->cmd.buswidth : SPI_NBITS_SINGLE;
+       int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE;
        int addrlen = op->addr.nbytes;
        int flex_mode = 1;
 
@@ -981,7 +981,7 @@ static int bcm_qspi_exec_mem_op(struct spi_mem *mem,
        if (mspi_read)
                return bcm_qspi_mspi_exec_mem_op(spi, op);
 
-       ret = bcm_qspi_bspi_set_mode(qspi, op, -1);
+       ret = bcm_qspi_bspi_set_mode(qspi, op, 0);
 
        if (!ret)
                ret = bcm_qspi_bspi_exec_mem_op(spi, op);
index 840b1b8ff3dcbf644eff61ad239d9917dcae1406..dfdcebb38830a795e8a3676d19fc788cca1dcef5 100644 (file)
@@ -319,6 +319,13 @@ static void bcm2835_spi_reset_hw(struct spi_controller *ctlr)
                BCM2835_SPI_CS_INTD |
                BCM2835_SPI_CS_DMAEN |
                BCM2835_SPI_CS_TA);
+       /*
+        * Transmission sometimes breaks unless the DONE bit is written at the
+        * end of every transfer.  The spec says it's a RO bit.  Either the
+        * spec is wrong and the bit is actually of type RW1C, or it's a
+        * hardware erratum.
+        */
+       cs |= BCM2835_SPI_CS_DONE;
        /* and reset RX/TX FIFOS */
        cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX;
 
@@ -477,7 +484,9 @@ static void bcm2835_spi_transfer_prologue(struct spi_controller *ctlr,
                bcm2835_wr_fifo_count(bs, bs->rx_prologue);
                bcm2835_wait_tx_fifo_empty(bs);
                bcm2835_rd_fifo_count(bs, bs->rx_prologue);
-               bcm2835_spi_reset_hw(ctlr);
+               bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_RX
+                                                 | BCM2835_SPI_CS_CLEAR_TX
+                                                 | BCM2835_SPI_CS_DONE);
 
                dma_sync_single_for_device(ctlr->dma_rx->device->dev,
                                           sg_dma_address(&tfr->rx_sg.sgl[0]),
@@ -498,7 +507,8 @@ static void bcm2835_spi_transfer_prologue(struct spi_controller *ctlr,
                                                  | BCM2835_SPI_CS_DMAEN);
                bcm2835_wr_fifo_count(bs, tx_remaining);
                bcm2835_wait_tx_fifo_empty(bs);
-               bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_TX);
+               bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_TX
+                                                 | BCM2835_SPI_CS_DONE);
        }
 
        if (likely(!bs->tx_spillover)) {
index 9651679ee7f7330a7f68ca469fb7d43226dfb515..90e7b789da3b07ee134333468a2ac782ff2ca87f 100644 (file)
@@ -19,6 +19,7 @@ struct spi_pci_desc {
        int     (*setup)(struct dw_spi *);
        u16     num_cs;
        u16     bus_num;
+       u32     max_freq;
 };
 
 static struct spi_pci_desc spi_pci_mid_desc_1 = {
@@ -33,6 +34,12 @@ static struct spi_pci_desc spi_pci_mid_desc_2 = {
        .bus_num = 1,
 };
 
+static struct spi_pci_desc spi_pci_ehl_desc = {
+       .num_cs = 1,
+       .bus_num = -1,
+       .max_freq = 100000000,
+};
+
 static int spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 {
        struct dw_spi *dws;
@@ -65,6 +72,7 @@ static int spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
        if (desc) {
                dws->num_cs = desc->num_cs;
                dws->bus_num = desc->bus_num;
+               dws->max_freq = desc->max_freq;
 
                if (desc->setup) {
                        ret = desc->setup(dws);
@@ -125,8 +133,14 @@ static const struct pci_device_id pci_ids[] = {
        { PCI_VDEVICE(INTEL, 0x0800), (kernel_ulong_t)&spi_pci_mid_desc_1},
        /* Intel MID platform SPI controller 2 */
        { PCI_VDEVICE(INTEL, 0x0812), (kernel_ulong_t)&spi_pci_mid_desc_2},
+       /* Intel Elkhart Lake PSE SPI controllers */
+       { PCI_VDEVICE(INTEL, 0x4b84), (kernel_ulong_t)&spi_pci_ehl_desc},
+       { PCI_VDEVICE(INTEL, 0x4b85), (kernel_ulong_t)&spi_pci_ehl_desc},
+       { PCI_VDEVICE(INTEL, 0x4b86), (kernel_ulong_t)&spi_pci_ehl_desc},
+       { PCI_VDEVICE(INTEL, 0x4b87), (kernel_ulong_t)&spi_pci_ehl_desc},
        {},
 };
+MODULE_DEVICE_TABLE(pci, pci_ids);
 
 static struct pci_driver dw_spi_driver = {
        .name =         DRIVER_NAME,
index 53335ccc98f61812d30e78eea8e036b28314cfe0..545fc8189fb0af39b98fc762511d2b417fea437c 100644 (file)
@@ -886,9 +886,11 @@ static irqreturn_t dspi_interrupt(int irq, void *dev_id)
                                        trans_mode);
                        }
                }
+
+               return IRQ_HANDLED;
        }
 
-       return IRQ_HANDLED;
+       return IRQ_NONE;
 }
 
 static const struct of_device_id fsl_dspi_dt_ids[] = {
index b32c77df5d49cf8acd5c253d9f6965909383e834..4e99a0f25c298874f353f555f4a2143edf0b510d 100644 (file)
@@ -214,6 +214,7 @@ static void uniphier_spi_setup_transfer(struct spi_device *spi,
        if (!priv->is_save_param || priv->mode != spi->mode) {
                uniphier_spi_set_mode(spi);
                priv->mode = spi->mode;
+               priv->is_save_param = false;
        }
 
        if (!priv->is_save_param || priv->bits_per_word != t->bits_per_word) {
index c6bee67decb5012ed0abb97f717da80df04da2b8..d812a215ae5cf20b599bd0e93a48f25a7e41a0f6 100644 (file)
@@ -695,7 +695,7 @@ static int zynq_qspi_probe(struct platform_device *pdev)
        ctlr->setup = zynq_qspi_setup_op;
        ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
        ctlr->dev.of_node = np;
-       ret = spi_register_controller(ctlr);
+       ret = devm_spi_register_controller(&pdev->dev, ctlr);
        if (ret) {
                dev_err(&pdev->dev, "spi_register_master failed\n");
                goto clk_dis_all;