drm/i915: move and group fdi members under display.fdi
authorJani Nikula <jani.nikula@intel.com>
Mon, 29 Aug 2022 13:18:17 +0000 (16:18 +0300)
committerJani Nikula <jani.nikula@intel.com>
Wed, 31 Aug 2022 12:20:07 +0000 (15:20 +0300)
Move display fdi related members under drm_i915_private display
sub-struct.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/b66fe7cf2c6f9e5b7bbfcaff40400492ac706721.1661779055.git.jani.nikula@intel.com
drivers/gpu/drm/i915/display/intel_crt.c
drivers/gpu/drm/i915/display/intel_display_core.h
drivers/gpu/drm/i915/display/intel_fdi.c
drivers/gpu/drm/i915/i915_drv.h

index 760b5788eb4343af4d3f4424b680b25e4b513662..6c555555b7bfe420f1aa7ad884d4fc5089d52b21 100644 (file)
@@ -1110,8 +1110,8 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
                u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
                                 FDI_RX_LINK_REVERSAL_OVERRIDE;
 
-               dev_priv->fdi_rx_config = intel_de_read(dev_priv,
-                                                       FDI_RX_CTL(PIPE_A)) & fdi_config;
+               dev_priv->display.fdi.rx_config = intel_de_read(dev_priv,
+                                                               FDI_RX_CTL(PIPE_A)) & fdi_config;
        }
 
        intel_crt_reset(&crt->base.base);
index 1f25e22496dbd86f392c10033cd18cdda96eda8a..0aeebf169ba6d450df495ff7dc24f791a8a0f84a 100644 (file)
@@ -299,6 +299,11 @@ struct intel_display {
                struct work_struct suspend_work;
        } fbdev;
 
+       struct {
+               unsigned int pll_freq;
+               u32 rx_config;
+       } fdi;
+
        struct {
                /*
                 * Base address of where the gmbus and gpio blocks are located
index 03ad5f5c8417f10ae7c499a881c3709020d45c35..f67dd4f05babc8cc1d83d136f7f034c1c6f0a1e9 100644 (file)
@@ -210,14 +210,14 @@ void intel_fdi_pll_freq_update(struct drm_i915_private *i915)
                u32 fdi_pll_clk =
                        intel_de_read(i915, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
 
-               i915->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
+               i915->display.fdi.pll_freq = (fdi_pll_clk + 2) * 10000;
        } else if (IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915)) {
-               i915->fdi_pll_freq = 270000;
+               i915->display.fdi.pll_freq = 270000;
        } else {
                return;
        }
 
-       drm_dbg(&i915->drm, "FDI PLL freq=%d\n", i915->fdi_pll_freq);
+       drm_dbg(&i915->drm, "FDI PLL freq=%d\n", i915->display.fdi.pll_freq);
 }
 
 int intel_fdi_link_freq(struct drm_i915_private *i915,
@@ -226,7 +226,7 @@ int intel_fdi_link_freq(struct drm_i915_private *i915,
        if (HAS_DDI(i915))
                return pipe_config->port_clock; /* SPLL */
        else
-               return i915->fdi_pll_freq;
+               return i915->display.fdi.pll_freq;
 }
 
 int ilk_fdi_compute_config(struct intel_crtc *crtc,
@@ -789,7 +789,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
                       FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 
        /* Enable the PCH Receiver FDI PLL */
-       rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
+       rx_ctl_val = dev_priv->display.fdi.rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
                     FDI_RX_PLL_ENABLE |
                     FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
        intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
index 0746793200562266096acdede2bcab0aed0ea52c..a03b8e676a227b0eea42f98989e030d08a1fec4c 100644 (file)
@@ -291,7 +291,6 @@ struct drm_i915_private {
 
        unsigned int max_dotclk_freq;
        unsigned int hpll_freq;
-       unsigned int fdi_pll_freq;
        unsigned int czclk_freq;
 
        struct {
@@ -364,8 +363,6 @@ struct drm_i915_private {
        struct drm_property *broadcast_rgb_property;
        struct drm_property *force_audio_property;
 
-       u32 fdi_rx_config;
-
        /*
         * Shadows for CHV DPLL_MD regs to keep the state
         * checker somewhat working in the presence hardware