drm/i915/execlists: Use vfunc to check engine submission mode
authorMichal Wajdeczko <michal.wajdeczko@intel.com>
Mon, 28 Oct 2019 16:45:20 +0000 (16:45 +0000)
committerChris Wilson <chris@chris-wilson.co.uk>
Mon, 28 Oct 2019 20:40:07 +0000 (20:40 +0000)
While processing CSB there is no need to look at GuC submission
settings, just check if engine is configured for execlists mode.

While today GuC submission is disabled it's settings are still
based on modparam values that might not correctly reflect actual
submission status in case of any fallback. Until that is fully
fixed, use alternate method to confirm that engine really runs in
execlists mode by comparing set_default_submission vfunc.

v2: add other immediate use of new helper

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
Reviewed-by: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191028164520.31772-1-michal.wajdeczko@intel.com
drivers/gpu/drm/i915/gt/intel_lrc.c
drivers/gpu/drm/i915/gt/intel_lrc.h
drivers/gpu/drm/i915/i915_perf.c

index c153d83511b7fc88f2c593bfb1d68e0db68ccc6e..2f474c1f5c54a7bb99868d62a803a7d91ca05bdc 100644 (file)
@@ -2015,7 +2015,7 @@ static void process_csb(struct intel_engine_cs *engine)
         */
        GEM_BUG_ON(!tasklet_is_locked(&execlists->tasklet) &&
                   !reset_in_progress(execlists));
-       GEM_BUG_ON(USES_GUC_SUBMISSION(engine->i915));
+       GEM_BUG_ON(!intel_engine_in_execlists_submission_mode(engine));
 
        /*
         * Note that csb_write, csb_status may be either in HWSP or mmio.
@@ -4705,6 +4705,13 @@ void intel_lr_context_reset(struct intel_engine_cs *engine,
        __execlists_update_reg_state(ce, engine);
 }
 
+bool
+intel_engine_in_execlists_submission_mode(const struct intel_engine_cs *engine)
+{
+       return engine->set_default_submission ==
+              intel_execlists_set_default_submission;
+}
+
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 #include "selftest_lrc.c"
 #endif
index 99dc576a4e25aa626e7994e00813402a60bd1f4e..7860787cb856b3444dcca9858738ff4539da19fb 100644 (file)
@@ -145,4 +145,7 @@ struct intel_engine_cs *
 intel_virtual_engine_get_sibling(struct intel_engine_cs *engine,
                                 unsigned int sibling);
 
+bool
+intel_engine_in_execlists_submission_mode(const struct intel_engine_cs *engine);
+
 #endif /* _INTEL_LRC_H_ */
index 38d3de2dfaa6b37f74e4729a533d6fedb0ecd99d..a807b6f0dfa3cbebe78ac18b18bfa302ad9dcac6 100644 (file)
@@ -1261,7 +1261,11 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
        case 8:
        case 9:
        case 10:
-               if (USES_GUC_SUBMISSION(ce->engine->i915)) {
+               if (intel_engine_in_execlists_submission_mode(ce->engine)) {
+                       stream->specific_ctx_id_mask =
+                               (1U << GEN8_CTX_ID_WIDTH) - 1;
+                       stream->specific_ctx_id = stream->specific_ctx_id_mask;
+               } else {
                        /*
                         * When using GuC, the context descriptor we write in
                         * i915 is read by GuC and rewritten before it's
@@ -1281,10 +1285,6 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
                         */
                        stream->specific_ctx_id_mask =
                                (1U << (GEN8_CTX_ID_WIDTH - 1)) - 1;
-               } else {
-                       stream->specific_ctx_id_mask =
-                               (1U << GEN8_CTX_ID_WIDTH) - 1;
-                       stream->specific_ctx_id = stream->specific_ctx_id_mask;
                }
                break;