Merge tag 'v5.4-rc3' into spi-5.4

Linux 5.4-rc3

diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index bec758e978fb122e5b954081eda5394b2f4f3b2e..7bb018eb67d01b2d70d5b56fef03c11f349da8df 100644 (file)
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -707,7 +707,7 @@ static irqreturn_t dspi_interrupt(int irq, void *dev_id)
        regmap_read(dspi->regmap, SPI_SR, &spi_sr);
        regmap_write(dspi->regmap, SPI_SR, spi_sr);
 
-       if (!(spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)))
+       if (!(spi_sr & SPI_SR_EOQF))
                return IRQ_NONE;
 
        if (dspi_rxtx(dspi) == 0) {
@@ -1114,6 +1114,9 @@ static int dspi_probe(struct platform_device *pdev)
 
        dspi_init(dspi);
 
+       if (dspi->devtype_data->trans_mode == DSPI_TCFQ_MODE)
+               goto poll_mode;
+
        dspi->irq = platform_get_irq(pdev, 0);
        if (dspi->irq <= 0) {
                dev_info(&pdev->dev,

diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
index d08e9324140e4dd9fd681fbfb6fc37285599053e..3528ed5eea9b55e51594b235d4e4305e4835cafc 100644 (file)
--- a/drivers/spi/spi-fsl-lpspi.c
+++ b/drivers/spi/spi-fsl-lpspi.c
@@ -938,7 +938,7 @@ static int fsl_lpspi_probe(struct platform_device *pdev)
        ret = pm_runtime_get_sync(fsl_lpspi->dev);
        if (ret < 0) {
                dev_err(fsl_lpspi->dev, "failed to enable clock\n");
-               return ret;
+               goto out_controller_put;
        }
 
        temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);

diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
index c02e24c01136719799fb140c9a937cc011869a8f..63c9f7edaf6cb323a766fdceb6c595334e25e336 100644 (file)
--- a/drivers/spi/spi-fsl-qspi.c
+++ b/drivers/spi/spi-fsl-qspi.c
@@ -63,6 +63,11 @@
 #define QUADSPI_IPCR                   0x08
 #define QUADSPI_IPCR_SEQID(x)          ((x) << 24)
 
+#define QUADSPI_FLSHCR                 0x0c
+#define QUADSPI_FLSHCR_TCSS_MASK       GENMASK(3, 0)
+#define QUADSPI_FLSHCR_TCSH_MASK       GENMASK(11, 8)
+#define QUADSPI_FLSHCR_TDH_MASK                GENMASK(17, 16)
+
 #define QUADSPI_BUF3CR                 0x1c
 #define QUADSPI_BUF3CR_ALLMST_MASK     BIT(31)
 #define QUADSPI_BUF3CR_ADATSZ(x)       ((x) << 8)
@@ -95,6 +100,9 @@
 #define QUADSPI_FR                     0x160
 #define QUADSPI_FR_TFF_MASK            BIT(0)
 
+#define QUADSPI_RSER                   0x164
+#define QUADSPI_RSER_TFIE              BIT(0)
+
 #define QUADSPI_SPTRCLR                        0x16c
 #define QUADSPI_SPTRCLR_IPPTRC         BIT(8)
 #define QUADSPI_SPTRCLR_BFPTRC         BIT(0)
@@ -112,9 +120,6 @@
 #define QUADSPI_LCKER_LOCK             BIT(0)
 #define QUADSPI_LCKER_UNLOCK           BIT(1)
 
-#define QUADSPI_RSER                   0x164
-#define QUADSPI_RSER_TFIE              BIT(0)
-
 #define QUADSPI_LUT_BASE               0x310
 #define QUADSPI_LUT_OFFSET             (SEQID_LUT * 4 * 4)
 #define QUADSPI_LUT_REG(idx) \
@@ -181,6 +186,12 @@
  */
 #define QUADSPI_QUIRK_BASE_INTERNAL    BIT(4)
 
+/*
+ * Controller uses TDH bits in register QUADSPI_FLSHCR.
+ * They need to be set in accordance with the DDR/SDR mode.
+ */
+#define QUADSPI_QUIRK_USE_TDH_SETTING  BIT(5)
+
 struct fsl_qspi_devtype_data {
        unsigned int rxfifo;
        unsigned int txfifo;
@@ -209,7 +220,8 @@ static const struct fsl_qspi_devtype_data imx7d_data = {
        .rxfifo = SZ_128,
        .txfifo = SZ_512,
        .ahb_buf_size = SZ_1K,
-       .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK,
+       .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
+                 QUADSPI_QUIRK_USE_TDH_SETTING,
        .little_endian = true,
 };
 
@@ -217,7 +229,8 @@ static const struct fsl_qspi_devtype_data imx6ul_data = {
        .rxfifo = SZ_128,
        .txfifo = SZ_512,
        .ahb_buf_size = SZ_1K,
-       .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK,
+       .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
+                 QUADSPI_QUIRK_USE_TDH_SETTING,
        .little_endian = true,
 };
 
@@ -275,6 +288,11 @@ static inline int needs_amba_base_offset(struct fsl_qspi *q)
        return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
 }
 
+static inline int needs_tdh_setting(struct fsl_qspi *q)
+{
+       return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
+}
+
 /*
  * An IC bug makes it necessary to rearrange the 32-bit data.
  * Later chips, such as IMX6SLX, have fixed this bug.
@@ -710,6 +728,16 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q)
        qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
                    base + QUADSPI_MCR);
 
+       /*
+        * Previous boot stages (BootROM, bootloader) might have used DDR
+        * mode and did not clear the TDH bits. As we currently use SDR mode
+        * only, clear the TDH bits if necessary.
+        */
+       if (needs_tdh_setting(q))
+               qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &
+                           ~QUADSPI_FLSHCR_TDH_MASK,
+                           base + QUADSPI_FLSHCR);
+
        reg = qspi_readl(q, base + QUADSPI_SMPR);
        qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
                        | QUADSPI_SMPR_FSPHS_MASK

diff --git a/drivers/spi/spi-gpio.c b/drivers/spi/spi-gpio.c
index 1d3e23ec20a61fd926d29585fbd29d4d9d9d1593..f9c5bbb747142559be6700281dc56b958179a27b 100644 (file)
--- a/drivers/spi/spi-gpio.c
+++ b/drivers/spi/spi-gpio.c
@@ -371,8 +371,10 @@ static int spi_gpio_probe(struct platform_device *pdev)
                return -ENOMEM;
 
        status = devm_add_action_or_reset(&pdev->dev, spi_gpio_put, master);
-       if (status)
+       if (status) {
+               spi_master_put(master);
                return status;
+       }
 
        if (of_id)
                status = spi_gpio_probe_dt(pdev, master);

diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
index f48563c09b97cdb63495212f2862797f96e0958e..a736fdf4711965e5c0418dfa8e9ccee2d079d962 100644 (file)
--- a/drivers/spi/spi-mxic.c
+++ b/drivers/spi/spi-mxic.c
@@ -145,8 +145,8 @@
 #define LWR_SUSP_CTRL_EN       BIT(31)
 
 #define DMAS_CTRL              0x9c
-#define DMAS_CTRL_DIR_READ     BIT(31)
-#define DMAS_CTRL_EN           BIT(30)
+#define DMAS_CTRL_EN           BIT(31)
+#define DMAS_CTRL_DIR_READ     BIT(30)
 
 #define DATA_STROB             0xa0
 #define DATA_STROB_EDO_EN      BIT(2)
@@ -275,7 +275,7 @@ static void mxic_spi_hw_init(struct mxic_spi *mxic)
        writel(0, mxic->regs + HC_EN);
        writel(0, mxic->regs + LRD_CFG);
        writel(0, mxic->regs + LRD_CTRL);
-       writel(HC_CFG_NIO(1) | HC_CFG_TYPE(0, HC_CFG_TYPE_SPI_NAND) |
+       writel(HC_CFG_NIO(1) | HC_CFG_TYPE(0, HC_CFG_TYPE_SPI_NOR) |
               HC_CFG_SLV_ACT(0) | HC_CFG_MAN_CS_EN | HC_CFG_IDLE_SIO_LVL(1),
               mxic->regs + HC_CFG);
 }

diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c
index 6643ccdc250859747cf41f1796cc974aa08b3060..81c991c4ddbf635792480bf3b9d29595cfcccd6b 100644 (file)
--- a/drivers/spi/spi-orion.c
+++ b/drivers/spi/spi-orion.c
@@ -772,9 +772,6 @@ static int orion_spi_probe(struct platform_device *pdev)
        if (status < 0)
                goto out_rel_pm;
 
-       pm_runtime_mark_last_busy(&pdev->dev);
-       pm_runtime_put_autosuspend(&pdev->dev);
-
        master->dev.of_node = pdev->dev.of_node;
        status = spi_register_master(master);
        if (status < 0)

diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index bb6a14d1ab0f929d6e4573573be92db15e631acc..068c210376799cee413674a65ac16e1cc8540361 100644 (file)
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -1602,6 +1602,11 @@ static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
        return cs;
 }
 
+static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi)
+{
+       return MAX_DMA_LEN;
+}
+
 static int pxa2xx_spi_probe(struct platform_device *pdev)
 {
        struct device *dev = &pdev->dev;
@@ -1707,6 +1712,8 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
                } else {
                        controller->can_dma = pxa2xx_spi_can_dma;
                        controller->max_dma_len = MAX_DMA_LEN;
+                       controller->max_transfer_size =
+                               pxa2xx_spi_max_dma_transfer_size;
                }
        }
 

diff --git a/drivers/spi/spi-stm32-qspi.c b/drivers/spi/spi-stm32-qspi.c
index 9ac6f9fe13cf679f292c1ae2957917851bc5f34c..4e726929bb4f5e90d161d3933aa6075e6aff260f 100644 (file)
--- a/drivers/spi/spi-stm32-qspi.c
+++ b/drivers/spi/spi-stm32-qspi.c
@@ -528,7 +528,6 @@ static void stm32_qspi_release(struct stm32_qspi *qspi)
        stm32_qspi_dma_free(qspi);
        mutex_destroy(&qspi->lock);
        clk_disable_unprepare(qspi->clk);
-       spi_master_put(qspi->ctrl);
 }
 
 static int stm32_qspi_probe(struct platform_device *pdev)
@@ -626,6 +625,8 @@ static int stm32_qspi_probe(struct platform_device *pdev)
 
 err:
        stm32_qspi_release(qspi);
+       spi_master_put(qspi->ctrl);
+
        return ret;
 }
 

diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index f9502dbbb5c1e5a590289bf2818205f508d5b105..38699eaebcea17721a56a23c0add6368e6ed5406 100644 (file)
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1711,15 +1711,7 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
                spi->mode |= SPI_3WIRE;
        if (of_property_read_bool(nc, "spi-lsb-first"))
                spi->mode |= SPI_LSB_FIRST;
-
-       /*
-        * For descriptors associated with the device, polarity inversion is
-        * handled in the gpiolib, so all chip selects are "active high" in
-        * the logical sense, the gpiolib will invert the line if need be.
-        */
-       if (ctlr->use_gpio_descriptors)
-               spi->mode |= SPI_CS_HIGH;
-       else if (of_property_read_bool(nc, "spi-cs-high"))
+       if (of_property_read_bool(nc, "spi-cs-high"))
                spi->mode |= SPI_CS_HIGH;
 
        /* Device DUAL/QUAD mode */
@@ -1783,6 +1775,14 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
        }
        spi->chip_select = value;
 
+       /*
+        * For descriptors associated with the device, polarity inversion is
+        * handled in the gpiolib, so all gpio chip selects are "active high"
+        * in the logical sense, the gpiolib will invert the line if need be.
+        */
+       if ((ctlr->use_gpio_descriptors) && ctlr->cs_gpiods[spi->chip_select])
+               spi->mode |= SPI_CS_HIGH;
+
        /* Device speed */
        rc = of_property_read_u32(nc, "spi-max-frequency", &value);
        if (rc) {

diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
index 255786f2e84472a1a9f4ceb416dd27402bca2fc9..3ea9d8a3e6e8963c9da26717747f13baa9e3e9b8 100644 (file)
--- a/drivers/spi/spidev.c
+++ b/drivers/spi/spidev.c
@@ -627,6 +627,9 @@ static int spidev_release(struct inode *inode, struct file *filp)
                if (dofree)
                        kfree(spidev);
        }
+#ifdef CONFIG_SPI_SLAVE
+       spi_slave_abort(spidev->spi);
+#endif
        mutex_unlock(&device_list_lock);
 
        return 0;