Merge series "spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC...

Add QSPI controller support for Intel LGM SoC.

Patches to move move bindings over to
"Documentation/devicetree/bindings/spi/" directory and also added compatible
Support for Intel platform.

dt-bindings: spi: cadence-qspi: Add support for Intel lgm-qspi
(earlier patch mail thread and Ack-by)
link: "https://lore.kernel.org/lkml/5d6d1b85.1c69fb81.96938.0315@mx.google.com/"

Reference:
        https://lkml.org/lkml/2020/6/1/50
---
v9:
  - Vignesh review comments address and update
  - Retain the patchv4 move the binding documentation from mtd to spi
    directory.
  - Add intel's compatible string over the legacy documentation
  - Remove unused variable, CQSPI_SUPPORTS_MULTI_CHIPSELECT macro and check
  - YAML convertion patch alone dropped
v8:
  - As Mark suggested to add the dt-bindings documentation patches
    end of the series , so dropped.
v7:
  - Rob's review comments address and fixed dt-schema warning
  - Pratyush review comments address and update
  - DAC bit reset to 0 and 1 (enable/disable)
  - tested QSI-NOR flash mx25l12805d on LGM soc, it's working after disable DAC
  - Linus suggested to use 'num-cs' prperty instead of 'num-chipselect'
v6:
  - Rob's review comments update
  - add compatible string in properly aligned
  - remove cadence-qspi extra comaptible string in example
v5:
  - Rob's review comments update
  - const with single compatible string kept
v4:
  - Rob's review comments update
  - remove '|' no formatting to preserve
  - child node attributes follows under 'properties' under '@[0-9a-f]+$'.
v3:
  - Pratyush review comments update
  - CQSPI_SUPPORTS_MULTI_CHIPSELECT macro used instead of cqspi->use_direct_mode
  - disable DAC support placed in end of controller_init
v2:
  - Rob's review comments update for dt-bindings
  - add 'oneOf' for compatible selection
  - drop un-neccessary descriptions
  - add the cdns,is-decoded-cs and cdns,rclk-en properties as schema
  - remove 'allOf' in not required place
  - add AdditionalProperties false
  - add minItems/maxItems for qspi reset attributes

resend-v1:
  - As per Mark's suggestion , reorder the patch series 1-3 driver
    support patches, series 4-6 dt-bindings patches.
v1:
  - initial version

Ramuthevar Vadivel Murugan (5):
  spi: cadence-quadspi: Add QSPI support for Intel LGM SoC
  spi: cadence-quadspi: Disable the DAC for Intel LGM SoC
  spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC
  spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi
  dt-bindings: spi: cadence-qspi: Add support for Intel lgm-qspi

 .../bindings/{mtd => spi}/cadence-quadspi.txt      |  1 +
 drivers/spi/Kconfig                                |  2 +-
 drivers/spi/spi-cadence-quadspi.c                  | 24 ++++++++++++++++++----
 3 files changed, 22 insertions(+), 5 deletions(-)
 rename Documentation/devicetree/bindings/{mtd => spi}/cadence-quadspi.txt (97%)

--
2.11.0

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diff --git a/drivers/spi/spi-hisi-sfc-v3xx.c b/drivers/spi/spi-hisi-sfc-v3xx.c
index 4650b483a33d32c34f0c21d671af44ebab1d94dc..832b80e7ef67de102caf1c1d73e3318da1cb9dd0 100644 (file)
--- a/drivers/spi/spi-hisi-sfc-v3xx.c
+++ b/drivers/spi/spi-hisi-sfc-v3xx.c
@@ -465,14 +465,10 @@ static int hisi_sfc_v3xx_probe(struct platform_device *pdev)
 
        version = readl(host->regbase + HISI_SFC_V3XX_VERSION);
 
-       switch (version) {
-       case 0x351:
+       if (version >= 0x351)
                host->max_cmd_dword = 64;
-               break;
-       default:
+       else
                host->max_cmd_dword = 16;
-               break;
-       }
 
        ret = devm_spi_register_controller(dev, ctlr);
        if (ret)

diff --git a/drivers/spi/spi-qcom-qspi.c b/drivers/spi/spi-qcom-qspi.c
index 8863be37088456ad6c445ecbb8b797e9b5372a68..1dbcc410cd3541a6ff96c2758077d88ebedcc0c2 100644 (file)
--- a/drivers/spi/spi-qcom-qspi.c
+++ b/drivers/spi/spi-qcom-qspi.c
@@ -511,8 +511,7 @@ static int qcom_qspi_probe(struct platform_device *pdev)
        ret = platform_get_irq(pdev, 0);
        if (ret < 0)
                return ret;
-       ret = devm_request_irq(dev, ret, qcom_qspi_irq,
-                       IRQF_TRIGGER_HIGH, dev_name(dev), ctrl);
+       ret = devm_request_irq(dev, ret, qcom_qspi_irq, 0, dev_name(dev), ctrl);
        if (ret) {
                dev_err(dev, "Failed to request irq %d\n", ret);
                return ret;

diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index be0fb169d7a7855be353e550643b04af4dd8ccb2..db3e305d9ec472ad0313805fea9d37e9a7d2312b 100644 (file)
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -473,34 +473,14 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
  */
 static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
 {
-       u32 fthlv, half_fifo, packet;
+       u32 packet, bpw;
 
        /* data packet should not exceed 1/2 of fifo space */
-       half_fifo = (spi->fifo_size / 2);
-
-       /* data_packet should not exceed transfer length */
-       if (half_fifo > xfer_len)
-               packet = xfer_len;
-       else
-               packet = half_fifo;
-
-       if (spi->cur_bpw <= 8)
-               fthlv = packet;
-       else if (spi->cur_bpw <= 16)
-               fthlv = packet / 2;
-       else
-               fthlv = packet / 4;
+       packet = clamp(xfer_len, 1U, spi->fifo_size / 2);
 
        /* align packet size with data registers access */
-       if (spi->cur_bpw > 8)
-               fthlv += (fthlv % 2) ? 1 : 0;
-       else
-               fthlv += (fthlv % 4) ? (4 - (fthlv % 4)) : 0;
-
-       if (!fthlv)
-               fthlv = 1;
-
-       return fthlv;
+       bpw = DIV_ROUND_UP(spi->cur_bpw, 8);
+       return DIV_ROUND_UP(packet, bpw);
 }
 
 /**