iommu/vt-d: Add RPLS to quirk list to skip TE disabling
authorTejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Wed, 2 Mar 2022 04:32:56 +0000 (10:02 +0530)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Wed, 2 Mar 2022 22:06:30 +0000 (17:06 -0500)
The VT-d spec requires (10.4.4 Global Command Register, TE
field) that:

Hardware implementations supporting DMA draining must drain
any in-flight DMA read/write requests queued within the
Root-Complex before completing the translation enable
command and reflecting the status of the command through
the TES field in the Global Status register.

Unfortunately, some integrated graphic devices fail to do
so after some kind of power state transition. As the
result, the system might stuck in iommu_disable_translati
on(), waiting for the completion of TE transition.

This adds RPLS to a quirk list for those devices and skips
TE disabling if the qurik hits.

Link: https://gitlab.freedesktop.org/drm/intel/-/issues/4898
Tested-by: Raviteja Goud Talla <ravitejax.goud.talla@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302043256.191529-1-tejaskumarx.surendrakumar.upadhyay@intel.com
drivers/iommu/intel/iommu.c

index 92fea3fbbb114549888da4bec1900eafc44e1369..be9487516617a2e2e36cc623a9d77ce8de54840b 100644 (file)
@@ -5743,7 +5743,7 @@ static void quirk_igfx_skip_te_disable(struct pci_dev *dev)
        ver = (dev->device >> 8) & 0xff;
        if (ver != 0x45 && ver != 0x46 && ver != 0x4c &&
            ver != 0x4e && ver != 0x8a && ver != 0x98 &&
-           ver != 0x9a)
+           ver != 0x9a && ver != 0xa7)
                return;
 
        if (risky_device(dev))